 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| to all our customers information regarding change of names mentioned within this document, to renesas technology corp. on april 1 st 2003 the following semiconductor operations were transferred to renesas technology corporation: operat ions covering microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.). accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have all been changed to renesas technology corporation. except for our corporate trademar k, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. thank you for your understanding. renesas technology home page: www.renesas.com renesas technology corp. april 1, 2003 renesas technology corp.
hitachi 16-bit single-chip microcomputer h8s/2615 series h8s/2615 HD64F2615 hd6432615 hardware manual ? preliminary ? ade-602-309 rev. 0.5 03/10/03 hitachi, ltd. rev. 0.5, 03/03, page ii of xxvi cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products. rev. 0.5, 03/03, page iii of xxvi general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system?s operation is not guaranteed if they are accessed. rev. 0.5, 03/03, page iv of xxvi configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 11. index rev. 0.5, 03/03, page v of xxvi preface the h8s/2615 series are single-chip microcomputers made up of the high-speed h8s/2600 cpu as its core, and the peripheral functions required to configure a system. the h8s/2600 cpu has an instruction set that is compatible with the h8/300 and h8/300h cpus. this lsi is equipped with rom and ram memory, a 16-bit timer pulse unit (tpu), a watchdog timer (wdt), a serial communication interface (sci), a hitachi controller area network (hcan), an a/d converter, and i/o ports as on-chip peripheral modules required for system configuration. this lsi is suitable for use as an embedded microcomputer for high-level control systems. a single-power flash memory (f-ztat tm ) version is available for this lsi's rom. this provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. note: * f-ztat tm is a trademark of hitachi, ltd. target users: this manual was written for users who will be using the h8s/2615 series in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2615 series to the target users. refer to the h8s/2600 series, h8s/2000 series programming manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. rev. 0.5, 03/03, page vi of xxvi ? in order to understand the details of the cpu's functions read the h8s/2600 series, h8s/2000 series programming manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 17, list of registers. examples: register name: the following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/ h8s/2615 series manuals: manual title ade no. h8s/2615 series hardware manual this manual h8s/2600 series, h8s/2000 series programming manual ade-602-083 user's manuals for development tools: manual title ade no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual ade-702-247 h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series hitachi embedded workshop, hitachi debugging interface tutorial ade-702-231 hitachi embedded workshop user's manual ade-702-201 rev. 0.5, 03/03, page vii of xxvi contents section 1 overview............................................................................................1 1.1 features .................................................................................................................... ......... 1 1.2 internal block diagram..................................................................................................... 2 1.3 pin arrangement ............................................................................................................. .. 3 1.4 pin functions ............................................................................................................... ..... 4 section 2 cpu....................................................................................................9 2.1 features .................................................................................................................... ......... 9 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu .................................. 10 2.1.2 differences from h8/300 cpu ............................................................................ 11 2.1.3 differences from h8/300h cpu.......................................................................... 11 2.2 cpu operating modes ...................................................................................................... 12 2.2.1 normal mode....................................................................................................... 12 2.2.2 advanced mode................................................................................................... 13 2.3 address space............................................................................................................... .... 16 2.4 register configuration...................................................................................................... 17 2.4.1 general registers ................................................................................................. 18 2.4.2 program counter (pc) ......................................................................................... 19 2.4.3 extended control register (exr) ....................................................................... 19 2.4.4 condition-code register (ccr) .......................................................................... 20 2.4.5 multiply-accumulate register (mac) ................................................................ 21 2.4.6 initial values of cpu registers ........................................................................... 21 2.5 data formats................................................................................................................ ..... 22 2.5.1 general register data formats ............................................................................ 22 2.5.2 memory data formats ......................................................................................... 24 2.6 instruction set ............................................................................................................. ...... 25 2.6.1 table of instructions classified by function ....................................................... 26 2.6.2 basic instruction formats .................................................................................... 35 2.7 addressing modes and effective address calculation ..................................................... 37 2.7.1 register direct?rn............................................................................................. 37 2.7.2 register indirect?@ern .................................................................................... 37 2.7.3 register indirect with displacement?@(d:16, ern) or @(d:32, ern).............. 37 2.7.4 register indirect with post-increment or pre-decrement?@ern+ or @-ern.. 38 2.7.5 absolute address?@aa:8, @aa:16, @aa:24, or @aa:32.................................... 38 2.7.6 immediate?#xx:8, #xx:16, or #xx:32 ................................................................. 39 2.7.7 program-counter relative?@(d:8, pc) or @(d:16, pc).................................... 39 2.7.8 memory indirect?@@aa:8 ................................................................................ 39 2.7.9 effective address calculation ............................................................................. 40 2.8 processing states........................................................................................................... .... 43 rev. 0.5, 03/03, page viii of xxvi 2.9 usage notes ................................................................................................................. ..... 44 2.9.1 usage notes on bit manipulation instructions .................................................... 44 section 3 mcu operating modes .....................................................................45 3.1 operating mode selection ................................................................................................ 45 3.2 register descriptions ....................................................................................................... .46 3.2.1 mode control register (mdcr) ......................................................................... 46 3.2.2 system control register (syscr) ...................................................................... 46 3.3 pin functions in each operating mode ............................................................................ 48 3.3.1 pin functions ....................................................................................................... 48 3.4 address map ................................................................................................................. .... 49 section 4 exception handling ...........................................................................51 4.1 exception handling types and priority ............................................................................ 51 4.2 exception sources and exception vector table ............................................................... 51 4.3 reset ....................................................................................................................... .......... 53 4.3.1 reset exception handling.................................................................................... 53 4.3.2 interrupts after reset............................................................................................ 55 4.3.3 state of on-chip peripheral modules after reset release................................... 55 4.4 traces...................................................................................................................... .......... 56 4.5 interrupts .................................................................................................................. ......... 56 4.6 trap instruction............................................................................................................ ..... 57 4.7 stack status after exception handling.............................................................................. 58 4.8 usage note.................................................................................................................. ...... 59 section 5 interrupt controller............................................................................61 5.1 features .................................................................................................................... ......... 61 5.2 input/output pins ........................................................................................................... ... 63 5.3 register descriptions ....................................................................................................... .63 5.3.1 interrupt priority registers a, b, d to h, j, k, m (ipra, iprb, iprd to iprh, iprj, iprk, iprm) ............................................. 64 5.3.2 irq enable register (ier) .................................................................................. 65 5.3.3 irq sense control registers h and l (iscrh, iscrl)..................................... 66 5.3.4 irq status register (isr).................................................................................... 68 5.4 interrupt ................................................................................................................... ......... 68 5.4.1 external interrupts ............................................................................................... 68 5.4.2 internal interrupts................................................................................................. 69 5.5 interrupt exception handling vector table...................................................................... 69 5.6 interrupt control modes and interrupt operation ............................................................. 72 5.6.1 interrupt control mode 0 ..................................................................................... 72 5.6.2 interrupt control mode 2 ..................................................................................... 74 5.6.3 interrupt exception handling sequence .............................................................. 75 5.6.4 interrupt response times .................................................................................... 77 rev. 0.5, 03/03, page ix of xxvi 5.7 usage notes ................................................................................................................. ..... 78 5.7.1 contention between interrupt generation and disabling..................................... 78 5.7.2 instructions that disable interrupts ...................................................................... 79 5.7.3 when interrupts are disabled .............................................................................. 79 5.7.4 interrupts during execution of eepmov instruction.......................................... 80 section 6 bus controller....................................................................................81 6.1 basic timing................................................................................................................ ..... 81 6.1.1 on-chip memory access timing (rom, ram) ................................................ 81 6.1.2 on-chip peripheral module access timing........................................................ 82 6.1.3 on-chip hcan module access timing............................................................. 83 section 7 i/o ports .............................................................................................85 7.1 port 1...................................................................................................................... ........... 88 7.1.1 port 1 data direction register (p1ddr)............................................................. 88 7.1.2 port 1 data register (p1dr)................................................................................ 88 7.1.3 port 1 register (port1)...................................................................................... 89 7.1.4 pin functions ....................................................................................................... 89 7.2 port 4...................................................................................................................... ........... 92 7.2.1 port 4 register (port4)...................................................................................... 92 7.3 port 9...................................................................................................................... ........... 92 7.3.1 port 9 register (port9)...................................................................................... 92 7.4 port a...................................................................................................................... .......... 93 7.4.1 port a data direction register (paddr) ........................................................... 93 7.4.2 port a data register (padr).............................................................................. 94 7.4.3 port a register (porta) .................................................................................... 94 7.4.4 port a pull-up mos control register (papcr) ................................................ 95 7.4.5 port a open-drain control register (paodr) .................................................. 95 7.4.6 pin functions ....................................................................................................... 96 7.5 port b ...................................................................................................................... .......... 96 7.5.1 port b data direction register (pbddr)............................................................ 97 7.5.2 port b data register (pbdr) .............................................................................. 97 7.5.3 port b register (portb) .................................................................................... 98 7.5.4 port b pull-up mos control register (pbpcr)................................................. 98 7.5.5 port b open-drain control register (pbodr)................................................... 99 7.5.6 pin functions ....................................................................................................... 99 7.6 port c ...................................................................................................................... .......... 101 7.6.1 port c data direction register (pcddr)............................................................ 101 7.6.2 port c data register (pcdr) .............................................................................. 102 7.6.3 port c register (portc) .................................................................................... 103 7.6.4 port c pull-up mos control register (pcpcr)................................................. 103 7.6.5 port c open-drain control register (pcodr)................................................... 104 7.6.6 pin functions ....................................................................................................... 104 rev. 0.5, 03/03, page x of xxvi 7.7 port d...................................................................................................................... .......... 106 7.7.1 port d data direction register (pdddr) ........................................................... 106 7.7.2 port d data register (pddr).............................................................................. 107 7.7.3 port d register (portd) .................................................................................... 107 7.7.4 port d pull-up mos control register (pdpcr) ................................................. 108 7.7.5 pin function......................................................................................................... 108 7.8 port f...................................................................................................................... ........... 108 7.8.1 port f data direction register (pfddr) ............................................................ 108 7.8.2 port f data register (pfdr) ............................................................................... 109 7.8.3 port f register (portf) ..................................................................................... 110 7.8.4 pin functions ....................................................................................................... 110 section 8 16-bit timer pulse unit (tpu) .........................................................113 8.1 features .................................................................................................................... ......... 113 8.2 input/output pins ........................................................................................................... ... 117 8.3 register descriptions ....................................................................................................... . 118 8.3.1 timer control register (tcr)............................................................................. 120 8.3.2 timer mode register (tmdr) ............................................................................ 125 8.3.3 timer i/o control register (tior) ..................................................................... 127 8.3.4 timer interrupt enable register (tier) .............................................................. 144 8.3.5 timer status register (tsr)................................................................................ 145 8.3.6 timer counter (tcnt)........................................................................................ 148 8.3.7 timer general register (tgr) ............................................................................ 148 8.3.8 timer start register (tstr)................................................................................ 148 8.3.9 timer synchro register (tsyr) ......................................................................... 149 8.4 operation ................................................................................................................... ....... 150 8.4.1 basic functions.................................................................................................... 150 8.4.2 synchronous operation........................................................................................ 156 8.4.3 buffer operation .................................................................................................. 157 8.4.4 cascaded operation ............................................................................................. 161 8.4.5 pwm modes ........................................................................................................ 162 8.4.6 phase counting mode .......................................................................................... 167 8.5 interrupts .................................................................................................................. ......... 173 8.6 a/d converter activation................................................................................................. 175 8.7 operation timing............................................................................................................ .. 176 8.7.1 input/output timing ............................................................................................ 176 8.7.2 interrupt signal timing........................................................................................ 180 8.8 usage notes ................................................................................................................. ..... 183 8.8.1 module stop mode setting .................................................................................. 183 8.8.2 input clock restrictions ...................................................................................... 183 8.8.3 caution on period setting .................................................................................... 184 8.8.4 contention between tcnt write and clear operations..................................... 184 8.8.5 contention between tcnt write and increment operations.............................. 185 rev. 0.5, 03/03, page xi of xxvi 8.8.6 contention between tgr write and compare match ......................................... 185 8.8.7 contention between buffer register write and compare match ........................ 186 8.8.8 contention between tgr read and input capture.............................................. 187 8.8.9 contention between tgr write and input capture............................................. 187 8.8.10 contention between buffer register write and input capture ............................ 188 8.8.11 contention between overflow/underflow and counter clearing........................ 189 8.8.12 contention between tcnt write and overflow/underflow............................... 190 8.8.13 multiplexing of i/o pins ...................................................................................... 190 8.8.14 interrupts in module stop mode.......................................................................... 190 section 9 watchdog timer (wdt)....................................................................191 9.1 features .................................................................................................................... ......... 191 9.2 register descriptions ....................................................................................................... . 193 9.2.1 timer counter (tcnt)........................................................................................ 193 9.2.2 timer control/status register (tcsr)................................................................ 193 9.2.3 reset control/status register (rstcsr) ............................................................ 197 9.3 operation ................................................................................................................... ....... 198 9.3.1 watchdog timer mode ........................................................................................ 198 9.3.2 interval timer mode ............................................................................................ 200 9.4 interrupt sources........................................................................................................... .... 200 9.5 usage notes ................................................................................................................. ..... 200 9.5.1 notes on register access..................................................................................... 200 9.5.2 contention between timer counter (tcnt) write and increment ..................... 201 9.5.3 changing value of cks2 to cks0...................................................................... 202 9.5.4 switching between watchdog timer mode and interval timer mode................ 202 9.5.5 internal reset in watchdog timer mode............................................................. 202 9.5.6 ovf flag clearing in interval timer mode ........................................................ 202 section 10 serial communication interface (sci) ............................................203 10.1 features ................................................................................................................... .......... 203 10.2 input/output pins .......................................................................................................... .... 205 10.3 register descriptions ...................................................................................................... .. 205 10.3.1 receive shift register (rsr) .............................................................................. 206 10.3.2 receive data register (rdr) .............................................................................. 206 10.3.3 transmit data register (tdr)............................................................................. 206 10.3.4 transmit shift register (tsr) ............................................................................. 206 10.3.5 serial mode register (smr)................................................................................ 207 10.3.6 serial control register (scr).............................................................................. 210 10.3.7 serial status register (ssr) ................................................................................ 212 10.3.8 smart card mode register (scmr) .................................................................... 217 10.3.9 bit rate register (brr) ...................................................................................... 218 10.4 operation in asynchronous mode .................................................................................... 225 10.4.1 data transfer format........................................................................................... 225 rev. 0.5, 03/03, page xii of xxvi 10.4.2 receive data sampling timing and reception margin in asynchronous mode 227 10.4.3 clock.................................................................................................................... 228 10.4.4 sci initialization (asynchronous mode) ............................................................. 229 10.4.5 data transmission (asynchronous mode)........................................................... 230 10.4.6 serial data reception (asynchronous mode)...................................................... 232 10.5 multiprocessor communication function......................................................................... 236 10.5.1 multiprocessor serial data transmission ............................................................ 238 10.5.2 multiprocessor serial data reception ................................................................. 239 10.6 operation in clocked synchronous mode ........................................................................ 242 10.6.1 clock.................................................................................................................... 242 10.6.2 sci initialization (clocked synchronous mode) ................................................. 243 10.6.3 serial data transmission (clocked synchronous mode) .................................... 244 10.6.4 serial data reception (clocked synchronous mode).......................................... 247 10.6.5 simultaneous serial data transmission and reception (clocked synchronous mode) ............................................................................. 249 10.7 operation in smart card interface .................................................................................... 251 10.7.1 pin connection example...................................................................................... 251 10.7.2 data format (except for block transfer mode).................................................. 252 10.7.3 block transfer mode ........................................................................................... 253 10.7.4 receive data sampling timing and reception margin in smart card interface mode.............................................................................. 254 10.7.5 initialization ......................................................................................................... 25 5 10.7.6 data transmission (except for block transfer mode) ........................................ 255 10.7.7 serial data reception (except for block transfer mode) ................................... 258 10.7.8 clock output control........................................................................................... 259 10.8 interrupt sources.......................................................................................................... ..... 261 10.8.1 interrupts in normal serial communication interface mode .............................. 261 10.8.2 interrupts in smart card interface mode ............................................................. 262 10.9 usage notes ................................................................................................................ ...... 263 10.9.1 module stop mode setting .................................................................................. 263 10.9.2 break detection and processing .......................................................................... 263 10.9.3 mark state and break detection .......................................................................... 263 10.9.4 receive error flags and transmit operations (clocked synchronous mode only) .................................................................... 263 section 11 hitachi controller area network (hcan) .....................................265 11.1 features ................................................................................................................... .......... 265 11.2 input/output pins .......................................................................................................... .... 267 11.3 register descriptions ...................................................................................................... .. 267 11.3.1 master control register (mcr)........................................................................... 268 11.3.2 general status register (gsr) ............................................................................ 269 11.3.3 bit configuration register (bcr) ....................................................................... 271 11.3.4 mailbox configuration register (mbcr) ........................................................... 273 rev. 0.5, 03/03, page xiii of xxvi 11.3.5 transmit wait register (txpr) .......................................................................... 274 11.3.6 transmit wait cancel register (txcr).............................................................. 275 11.3.7 transmit acknowledge register (txack) ........................................................ 276 11.3.8 abort acknowledge register (aback) ............................................................. 277 11.3.9 receive complete register (rxpr).................................................................... 278 11.3.10 remote request register (rfpr)........................................................................ 279 11.3.11 interrupt register (irr) ....................................................................................... 280 11.3.12 mailbox interrupt mask register (mbimr)........................................................ 283 11.3.13 interrupt mask register (imr) ............................................................................ 284 11.3.14 receive error counter (rec) .............................................................................. 285 11.3.15 transmit error counter (tec)............................................................................. 285 11.3.16 unread message status register (umsr) ........................................................... 286 11.3.17 local acceptance filter masks (lafml, lafmh)........................................... 287 11.3.18 message control (mc0 to mc15) ....................................................................... 289 11.3.19 message data (md0 to md15) ........................................................................... 291 11.3.20 hcan monitor register (hcanmon).............................................................. 291 11.4 operation .................................................................................................................. ........ 293 11.4.1 hardware and software resets ............................................................................ 293 11.4.2 initialization after hardware reset ...................................................................... 293 11.4.3 message transmission ......................................................................................... 299 11.4.4 message reception .............................................................................................. 302 11.4.5 hcan sleep mode .............................................................................................. 305 11.4.6 hcan halt mode ................................................................................................ 306 11.5 interrupt sources.......................................................................................................... ..... 307 11.6 can bus interface.......................................................................................................... .. 308 11.7 usage notes ................................................................................................................ ...... 308 11.7.1 module stop mode setting .................................................................................. 308 11.7.2 reset.................................................................................................................... . 308 11.7.3 hcan sleep mode .............................................................................................. 309 11.7.4 interrupts.............................................................................................................. 3 09 11.7.5 error counters...................................................................................................... 309 11.7.6 register access.................................................................................................... 309 11.7.7 hcan medium-speed mode .............................................................................. 309 11.7.8 register hold in standby modes ......................................................................... 309 11.7.9 use on bit manipulation instructions .................................................................. 309 11.7.10 hcan txcr operation...................................................................................... 310 section 12 a/d converter..................................................................................311 12.1 features ................................................................................................................... .......... 311 12.2 input/output pins .......................................................................................................... .... 313 12.3 register descriptions ...................................................................................................... .. 314 12.3.1 a/d data registers a to d (addra to addrd).............................................. 314 12.3.2 a/d control/status register (adcsr) ............................................................... 315 rev. 0.5, 03/03, page xiv of xxvi 12.3.3 a/d control register (adcr) ............................................................................ 317 12.4 operation .................................................................................................................. ........ 318 12.4.1 single mode......................................................................................................... 318 12.4.2 scan mode ........................................................................................................... 318 12.4.3 input sampling and a/d conversion time ......................................................... 319 12.4.4 external trigger input timing............................................................................. 321 12.5 interrupt sources.......................................................................................................... ..... 321 12.6 a/d conversion accuracy definitions ............................................................................. 322 12.7 usage notes ................................................................................................................ ...... 324 12.7.1 module stop mode setting .................................................................................. 324 12.7.2 permissible signal source impedance ................................................................. 324 12.7.3 influences on absolute accuracy ........................................................................ 324 12.7.4 range of analog power supply and other pin settings ...................................... 325 12.7.5 notes on board design ........................................................................................ 325 12.7.6 notes on noise countermeasures ........................................................................ 325 section 13 ram ................................................................................................327 section 14 rom ................................................................................................329 14.1 features ................................................................................................................... .......... 329 14.2 mode transitions ........................................................................................................... ... 330 14.3 block configuration........................................................................................................ .. 334 14.4 input/output pins .......................................................................................................... .... 335 14.5 register descriptions ...................................................................................................... .. 335 14.5.1 flash memory control register 1 (flmcr1)..................................................... 336 14.5.2 flash memory control register 2 (flmcr2)..................................................... 337 14.5.3 erase block register 1 (ebr1) ........................................................................... 337 14.5.4 ram emulation register (ramer)................................................................... 338 14.5.5 flash memory power control register (flpwcr) ............................................ 339 14.6 on-board programming modes........................................................................................ 339 14.6.1 boot mode ........................................................................................................... 340 14.6.2 programming/erasing in user program mode..................................................... 342 14.7 flash memory emulation in ram ................................................................................... 343 14.8 flash memory programming/erasing ............................................................................... 345 14.8.1 program/program-verify ..................................................................................... 345 14.8.2 erase/erase-verify............................................................................................... 347 14.8.3 interrupt handling when programming/erasing flash memory.......................... 347 14.9 program/erase protection ................................................................................................. 34 9 14.9.1 hardware protection ............................................................................................ 349 14.9.2 software protection.............................................................................................. 349 14.9.3 error protection.................................................................................................... 349 14.10 programmer mode ........................................................................................................... . 350 14.11 power-down states for flash memory............................................................................. 350 rev. 0.5, 03/03, page xv of xxvi section 15 clock pulse generator .....................................................................351 15.1 register descriptions ...................................................................................................... .. 352 15.1.1 system clock control register (sckcr) ........................................................... 352 15.1.2 low-power control register (lpwrcr) ........................................................... 353 15.2 oscillator................................................................................................................. .......... 354 15.2.1 connecting a crystal resonator........................................................................... 354 15.2.2 external clock input ............................................................................................ 355 15.3 pll circuit ................................................................................................................ ....... 357 15.4 subclock divider ........................................................................................................... ... 357 15.5 medium-speed clock divider .......................................................................................... 357 15.6 bus master clock selection circuit .................................................................................. 357 15.7 usage notes ................................................................................................................ ...... 358 15.7.1 note on crystal resonator ................................................................................... 358 15.7.2 note on board design.......................................................................................... 358 section 16 power-down modes ........................................................................361 16.1 register descriptions ...................................................................................................... .. 365 16.1.1 standby control register (sbycr) .................................................................... 365 16.1.2 low-power control register (lpwrcr) ........................................................... 367 16.1.3 module stop control registers a to c (mstpcra to mstpcrc)................... 368 16.2 medium-speed mode........................................................................................................ 37 0 16.3 sleep mode ................................................................................................................. ...... 371 16.3.1 transition to sleep mode..................................................................................... 371 16.3.2 clearing sleep mode............................................................................................ 371 16.4 software standby mode.................................................................................................... 37 2 16.4.1 transition to software standby mode ................................................................. 372 16.4.2 clearing software standby mode ........................................................................ 372 16.4.3 setting oscillation stabilization time after clearing software standby mode... 373 16.4.4 software standby mode application example.................................................... 373 16.5 hardware standby mode .................................................................................................. 374 16.5.1 transition to hardware standby mode ................................................................ 374 16.5.2 clearing hardware standby mode....................................................................... 375 16.5.3 hardware standby mode timings ....................................................................... 375 16.6 module stop mode ........................................................................................................... 376 16.7 watch mode................................................................................................................. ..... 376 16.7.1 transition to watch mode ................................................................................... 376 16.7.2 canceling watch mode........................................................................................ 376 16.8 subsleep mode.............................................................................................................. .... 377 16.8.1 transition to subsleep mode ............................................................................... 377 16.8.2 canceling subsleep mode.................................................................................... 377 16.9 subactive mode ............................................................................................................. ... 378 16.9.1 transition to subactive mode .............................................................................. 378 16.9.2 canceling subactive mode .................................................................................. 378 rev. 0.5, 03/03, page xvi of xxvi 16.10 direct transitions........................................................................................................ ...... 378 16.10.1 direct transitions from high-speed mode to subactive mode........................... 379 16.10.2 direct transitions from subactive mode to high-speed mode........................... 379 16.11 clock output disabling function .................................................................................. 379 16.12 usage notes ............................................................................................................... ....... 380 16.12.1 i/o port status...................................................................................................... 380 16.12.2 current consumption during oscillation stabilization wait period.................... 380 16.12.3 on-chip peripheral module interrupt.................................................................. 380 16.12.4 writing to mstpcr ............................................................................................ 380 section 17 list of registers...............................................................................381 17.1 register addresses (address order) ................................................................................. 382 17.2 register bits.............................................................................................................. ........ 395 17.3 register states in each operating mode........................................................................... 407 section 18 electrical characteristics .................................................................417 18.1 absolute maximum ratings ............................................................................................. 417 18.2 dc characteristics ......................................................................................................... ... 418 18.3 ac characteristics ......................................................................................................... ... 420 18.3.1 clock timing ....................................................................................................... 421 18.3.2 control signal timing ......................................................................................... 422 18.3.3 timing of on-chip peripheral modules .............................................................. 424 18.4 a/d conversion characteristics........................................................................................ 427 18.5 flash memory characteristics........................................................................................... 428 appendix .........................................................................................................431 a. i/o port states in each pin state....................................................................................... 431 b. product code lineup ........................................................................................................ 43 2 c. package dimensions ......................................................................................................... 43 3 index .........................................................................................................435 rev. 0.5, 03/03, page xvii of xxvi figures section 1 overview figure 1.1 internal block diagram ............................................................................................ .....2 figure 1.2 pin arrangement................................................................................................... .........3 section 2 cpu figure 2.1 exception vector table (normal mode) .....................................................................13 figure 2.2 stack structure in normal mode .................................................................................13 figure 2.3 exception vector table (advanced mode) .................................................................14 figure 2.4 stack structure in advanced mode .............................................................................15 figure 2.5 memory map ........................................................................................................ .......16 figure 2.6 cpu registers ..................................................................................................... ........17 figure 2.7 usage of general registers ........................................................................................ .18 figure 2.8 stack ............................................................................................................. ...............19 figure 2.9 general register data formats (1) ..............................................................................22 figure 2.9 general register data formats (2) ..............................................................................23 figure 2.10 memory data formats.............................................................................................. .24 figure 2.11 instruction formats (examples) ................................................................................36 figure 2.12 branch address specification in memory indirect mode .........................................40 figure 2.13 state transitions ................................................................................................ ........44 section 3 mcu operating modes figure 3.1 address map....................................................................................................... .........49 section 4 exception handling figure 4.1 reset sequence (advanced mode with on-chip rom enabled)................................54 figure 4.2 reset sequence (advanced mode with on-chip rom disabled: cannot be used in this lsi)......................................................................................... 55 figure 4.3 stack status after exception handling ........................................................................58 figure 4.4 operation when sp value is odd ................................................................................59 section 5 interrupt controller figure 5.1 block diagram of interrupt controller ........................................................................62 figure 5.2 block diagram of interrupts irq0 to irq5 ................................................................69 figure 5.3 flowchart of procedure up to interrupt acceptance in interrupt control mode 0......73 figure 5.4 flowchart of procedure up to interrupt acceptance in control mode 2.....................75 figure 5.5 interrupt exception handling ...................................................................................... 76 figure 5.6 contention between interrupt generation and disabling ............................................79 section 6 bus controller figure 6.1 on-chip memory access cycle..................................................................................81 figure 6.2 on-chip support module access cycle......................................................................82 figure 6.3 on-chip hcan module access cycle (wait states inserted) ...................................83 rev. 0.5, 03/03, page xviii of xxvi section 8 16-bit timer pulse unit (tpu) figure 8.1 block diagram of tpu.............................................................................................. 116 figure 8.2 example of counter operation setting procedure .................................................... 150 figure 8.3 free-running counter operation .............................................................................. 151 figure 8.4 periodic counter operation....................................................................................... 1 52 figure 8.5 example of setting procedure for waveform output by compare match................ 152 figure 8.6 example of 0 output/1 output operation ................................................................. 153 figure 8.7 example of toggle output operation ....................................................................... 153 figure 8.8 example of input capture operation setting procedure ........................................... 154 figure 8.9 example of input capture operation......................................................................... 155 figure 8.10 example of synchronous operation setting procedure .......................................... 156 figure 8.11 example of synchronous operation........................................................................ 157 figure 8.12 compare match buffer operation........................................................................... 158 figure 8.13 input capture buffer operation............................................................................... 158 figure 8.14 example of buffer operation setting procedure..................................................... 159 figure 8.15 example of buffer operation (1)............................................................................. 160 figure 8.16 example of buffer operation (2)............................................................................. 160 figure 8.17 cascaded operation setting procedure ................................................................... 161 figure 8.18 example of cascaded operation (1)........................................................................ 162 figure 8.19 example of cascaded operation (2)........................................................................ 162 figure 8.20 example of pwm mode setting procedure ............................................................ 164 figure 8.21 example of pwm mode operation (1) ................................................................... 164 figure 8.22 example of pwm mode operation (2) ................................................................... 165 figure 8.23 example of pwm mode operation (3) ................................................................... 166 figure 8.24 example of phase counting mode setting procedure............................................. 167 figure 8.25 example of phase counting mode 1 operation ...................................................... 168 figure 8.26 example of phase counting mode 2 operation ...................................................... 169 figure 8.27 example of phase counting mode 3 operation ...................................................... 170 figure 8.28 example of phase counting mode 4 operation ...................................................... 171 figure 8.29 phase counting mode application example........................................................... 173 figure 8.30 count timing in internal clock operation.............................................................. 176 figure 8.31 count timing in external clock operation............................................................. 176 figure 8.32 output compare output timing.............................................................................. 177 figure 8.33 input capture input signal timing.......................................................................... 177 figure 8.34 counter clear timing (compare match) ................................................................ 178 figure 8.35 counter clear timing (input capture) .................................................................... 178 figure 8.36 buffer operation timing (compare match)............................................................ 179 figure 8.37 buffer operation timing (input capture) ............................................................... 179 figure 8.38 tgi interrupt timing (compare match) ................................................................. 180 figure 8.39 tgi interrupt timing (input capture) ..................................................................... 180 figure 8.40 tciv interrupt setting timing................................................................................ 181 figure 8.41 tciu interrupt setting timing................................................................................ 181 figure 8.42 timing for status flag clearing by cpu ................................................................ 182 rev. 0.5, 03/03, page xix of xxvi figure 8.43 phase difference, overlap, and pulse width in phase counting mode ..................183 figure 8.44 contention between tcnt write and clear operations .........................................184 figure 8.45 contention between tcnt write and increment operations .................................185 figure 8.46 contention between tgr write and compare match.............................................186 figure 8.47 contention between buffer register write and compare match ............................186 figure 8.48 contention between tgr read and input capture .................................................187 figure 8.49 contention between tgr write and input capture ................................................188 figure 8.50 contention between buffer register write and input capture................................188 figure 8.51 contention between overflow and counter clearing..............................................189 figure 8.52 contention between tcnt write and overflow.....................................................190 section 9 watchdog timer (wdt) figure 9.1 block diagram of wdt_0 ........................................................................................192 figure 9.2 block diagram of wdt_1 ........................................................................................192 figure 9.3 (a) wdt_0 operation in watchdog timer mode .....................................................199 figure 9.3 (b) wdt_1 operation in watchdog timer mode .....................................................199 figure 9.4 writing to tcnt, tcsr, and rstcsr (example for wdt0).................................201 figure 9.5 contention between tcnt write and increment......................................................201 section 10 serial communication interface (sci) figure 10.1 block diagram of sci ............................................................................................. 204 figure 10.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) ..................................................225 figure 10.3 receive data sampling timing in asynchronous mode ........................................227 figure 10.4 relationship between output clock and transfer data phase (asynchronous mode) .............................................................................................22 8 figure 10.5 sample sci initialization flowchart .......................................................................229 figure 10.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit).....................................................230 figure 10.7 sample serial transmission flowchart ...................................................................231 figure 10.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit).....................................................232 figure 10.9 sample serial reception data flowchart (1) ..........................................................234 figure 10.9 sample serial reception data flowchart (2) ..........................................................235 figure 10.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) ...........................................237 figure 10.11 sample multiprocessor serial transmission flowchart ........................................238 figure 10.12 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) ..............................239 figure 10.13 sample multiprocessor serial reception flowchart (1)........................................240 figure 10.13 sample multiprocessor serial reception flowchart (2)........................................241 figure 10.14 data format in synchronous communication (for lsb-first).............................242 figure 10.15 sample sci initialization flowchart......................................................................243 figure 10.16 sample sci transmission operation in clocked synchronous mode ..................245 rev. 0.5, 03/03, page xx of xxvi figure 10.17 sample serial transmission flowchart ................................................................. 246 figure 10.18 example of sci operation in reception ............................................................... 247 figure 10.19 sample serial reception flowchart....................................................................... 248 figure 10.20 sample flowchart of simultaneous serial transmit and receive operations ...... 250 figure 10.21 schematic diagram of smart card interface pin connections.............................. 251 figure 10.22 normal smart card interface data format............................................................ 252 figure 10.23 direct convention (sdir = sinv = o/ e = 0) ...................................................... 252 figure 10.24 inverse convention (sdir = sinv = o/ e = 1)..................................................... 253 figure 10.25 receive data sampling timing in smart card interface mode (using clock of 372 times the transfer rate) ...................................................... 254 figure 10.26 retransfer operation in sci transmit mode......................................................... 256 figure 10.27 tend flag generation timing in transmission operation.................................. 256 figure 10.28 example of transmission processing flow........................................................... 257 figure 10.29 retransfer operation in sci receive mode .......................................................... 258 figure 10.30 example of reception processing flow ................................................................ 259 figure 10.31 timing for fixing clock output level.................................................................. 259 figure 10.32 clock halt and restart procedure ......................................................................... 260 section 11 hitachi controller area network (hcan) figure 11.1 hcan block diagram ............................................................................................ 266 figure 11.2 message control register configuration ................................................................ 289 figure 11.3 standard format .................................................................................................. .... 289 figure 11.4 extended format .................................................................................................. ... 289 figure 11.5 message data configuration ................................................................................... 291 figure 11.6 hardware reset flowchart ...................................................................................... 294 figure 11.7 software reset flowchart........................................................................................ 2 95 figure 11.8 detailed description of one bit .............................................................................. 296 figure 11.9 transmission flowchart .......................................................................................... 2 99 figure 11.10 transmit message cancellation flowchart ........................................................... 301 figure 11.11 reception flowchart............................................................................................. . 302 figure 11.12 unread message overwrite flowchart .................................................................. 304 figure 11.13 hcan sleep mode flowchart .............................................................................. 305 figure 11.14 hcan halt mode flowchart ................................................................................ 306 figure 11.15 high-speed interface using pca82c250 ............................................................. 308 section 12 a/d converter figure 12.1 block diagram of a/d converter ........................................................................... 312 figure 12.2 a/d conversion timing .......................................................................................... 31 9 figure 12.3 external trigger input timing ................................................................................ 321 figure 12.4 a/d conversion accuracy definitions.................................................................... 323 figure 12.5 a/d conversion accuracy definitions.................................................................... 323 figure 12.6 example of analog input circuit ............................................................................ 324 figure 12.7 example of analog input protection circuit ........................................................... 326 figure 12.8 analog input pin equivalent circuit ....................................................................... 326 rev. 0.5, 03/03, page xxi of xxvi section 14 rom figure 14.1 block diagram of flash memory ...........................................................................330 figure 14.2 flash memory state transitions..............................................................................331 figure 14.3 boot mode........................................................................................................ .......332 figure 14.4 user program mode ................................................................................................ 333 figure 14.5 flash memory block configuration........................................................................334 figure 14.6 programming/erasing flowchart example in user program mode ........................342 figure 14.7 flowchart for flash memory emulation in ram ...................................................343 figure 14.8 example of ram overlap operation......................................................................344 figure 14.9 program/program-verify flowchart........................................................................346 figure 14.10 erase/erase-verify flowchart ...............................................................................348 section 15 clock pulse generator figure 15.1 block diagram of clock pulse generator ...............................................................351 figure 15.2 connection of crystal resonator (example) ...........................................................354 figure 15.3 crystal resonator equivalent circuit ......................................................................355 figure 15.4 external clock input (examples) ............................................................................355 figure 15.5 external clock input timing...................................................................................356 figure 15.6 note on board design of oscillator circuit ............................................................358 figure 15.7 external circuitry recommended for pll circuit..................................................359 section 16 power-down modes figure 16.1 mode transition diagram........................................................................................36 2 figure 16.2 medium-speed mode transition and clearance timing.........................................371 figure 16.3 software standby mode application example........................................................374 figure 16.4 timing of transition to hardware standby mode...................................................375 figure 16.5 timing of recovery from hardware standby mode ...............................................375 section 18 electrical characteristics figure 18.1 output load circuit.............................................................................................. ...420 figure 18.2 system clock timing .............................................................................................. 421 figure 18.3 oscillation stabilization timing..............................................................................422 figure 18.4 reset input timing ............................................................................................... ...423 figure 18.5 interrupt input timing ........................................................................................... ..423 figure 18.6 i/o port input/output timing..................................................................................425 figure 18.7 tpu input/output timing .......................................................................................425 figure 18.8 tpu clock input timing.........................................................................................42 6 figure 18.9 sck clock input timing.........................................................................................42 6 figure 18.10 sci input/output timing (clocked synchronous mode)......................................426 figure 18.11 a/d converter external trigger input timing......................................................426 figure 18.12 hcan input/output timing..................................................................................427 appendix figure c.1 fp-80q package dimensions ...................................................................................433 rev. 0.5, 03/03, page xxii of xxvi rev. 0.5, 03/03, page xxiii of xxvi tables section 2 cpu table 2.1 instruction classification ............................................................................................ 25 table 2.2 operation notation.................................................................................................... ..26 table 2.3 data transfer instructions...........................................................................................2 7 table 2.4 arithmetic operations instructions (1) .......................................................................28 table 2.4 arithmetic operations instructions (2) .......................................................................29 table 2.5 logic operations instructions .....................................................................................30 table 2.6 shift instructions.................................................................................................... .....30 table 2.7 bit manipulation instructions (1)................................................................................31 table 2.7 bit manipulation instructions (2)................................................................................32 table 2.8 branch instructions ................................................................................................... ..33 table 2.9 system control instructions........................................................................................34 table 2.10 block data transfer instructions ............................................................................35 table 2.11 addressing modes ..................................................................................................37 table 2.12 absolute address access ranges ...........................................................................38 section 3 mcu operating modes table 3.1 mcu operating mode selection ................................................................................45 table 3.2 pin functions in each operating mode ......................................................................48 section 4 exception handling table 4.1 exception types and priority......................................................................................51 table 4.2 exception handling vector table...............................................................................52 table 4.3 status of ccr and exr after trace exception handling...........................................56 table 4.4 status of ccr and exr after trap instruction exception handling..........................57 section 5 interrupt controller table 5.1 pin configuration..................................................................................................... ...63 table 5.2 interrupt sources, vector addresses, and interrupt priorities.....................................70 table 5.3 interrupt control modes..............................................................................................7 2 table 5.4 interrupt response times ...........................................................................................77 table 5.5 number of states in interrupt handling routine execution status.............................78 section 7 i/o ports table 7.1 port functions ........................................................................................................ .....86 table 7.2 p17 pin function...................................................................................................... ...89 table 7.3 p16 pin function...................................................................................................... ...90 table 7.4 p15 pin function...................................................................................................... ...90 table 7.5 p14 pin function...................................................................................................... ...90 table 7.6 p13 pin function...................................................................................................... ...91 table 7.7 p12 pin function...................................................................................................... ...91 table 7.8 p11 pin function...................................................................................................... ...91 rev. 0.5, 03/03, page xxiv of xxvi table 7.9 p10 pin function...................................................................................................... ... 91 table 7.10 pa3 pin function.................................................................................................... 9 6 table 7.11 pa2 pin function.................................................................................................... 9 6 table 7.12 pa1 pin function.................................................................................................... 9 6 table 7.13 pa0 pin function.................................................................................................... 9 6 table 7.14 pb7 pin function .................................................................................................... 9 9 table 7.15 pb6 pin function .................................................................................................... 9 9 table 7.16 pb5 pin function .................................................................................................. 100 table 7.17 pb4 pin function .................................................................................................. 100 table 7.18 pb3 pin function .................................................................................................. 100 table 7.19 pb2 pin function .................................................................................................. 100 table 7.20 pb1 pin function .................................................................................................. 101 table 7.21 pb0 pin function .................................................................................................. 101 table 7.22 pc7 pin function .................................................................................................. 104 table 7.23 pc6 pin function .................................................................................................. 104 table 7.24 pc5 pin function .................................................................................................. 104 table 7.25 pc4 pin function .................................................................................................. 105 table 7.26 pc3 pin function .................................................................................................. 105 table 7.27 pc2 pin function .................................................................................................. 105 table 7.28 pc1 pin function .................................................................................................. 105 table 7.29 pc0 pin function .................................................................................................. 105 table 7.30 pdn pin function.................................................................................................. 108 table 7.31 pf7 pin function .................................................................................................. 110 table 7.32 pf6 pin function .................................................................................................. 110 table 7.33 pf5 pin function .................................................................................................. 110 table 7.34 pf4 pin function .................................................................................................. 111 table 7.35 pf3 pin function .................................................................................................. 111 table 7.36 pf2 pin function .................................................................................................. 111 table 7.37 pf1 pin function .................................................................................................. 111 table 7.38 pf0 pin function .................................................................................................. 111 section 8 16-bit timer pulse unit (tpu) table 8.1 tpu functions ......................................................................................................... . 114 table 8.2 pin configuration..................................................................................................... . 117 table 8.3 cclr0 to cclr2 (channels 0 and 3) ...................................................................... 121 table 8.4 cclr0 to cclr2 (channels 1, 2, 4, and 5) ............................................................. 121 table 8.5 tpsc0 to tpsc2 (channel 0) ................................................................................... 122 table 8.6 tpsc0 to tpsc2 (channel 1) ................................................................................... 122 table 8.7 tpsc0 to tpsc2 (channels 2).................................................................................. 123 table 8.8 tpsc0 to tpsc2 (channel 3) ................................................................................... 123 table 8.9 tpsc0 to tpsc2 (channel 4) ................................................................................... 124 table 8.10 tpsc0 to tpsc2 (channel 5) ............................................................................... 124 table 8.11 md0 to md3 ........................................................................................................ 126 rev. 0.5, 03/03, page xxv of xxvi table 8.12 tiorh_0 (channel 0) ..........................................................................................128 table 8.13 tiorl_0 (channel 0)............................................................................................129 table 8.14 tior_1 (channel 1) .............................................................................................130 table 8.15 tior_2 (channel 2) .............................................................................................131 table 8.16 tiorh_3 (channel 3) ..........................................................................................132 table 8.17 tiorl_3 (channel 3)...........................................................................................133 table 8.18 tior_4 (channel 4) .............................................................................................134 table 8.19 tior_5 (channel 5) .............................................................................................135 table 8.20 tiorh_0 (channel 0) ..........................................................................................136 table 8.21 tiorl_0 (channel 0)...........................................................................................137 table 8.22 tior_1 (channel 1) .............................................................................................138 table 8.23 tior_2 (channel 2) .............................................................................................139 table 8.24 tiorh_3 (channel 3) ..........................................................................................140 table 8.25 tiorl_3 (channel 3)...........................................................................................141 table 8.26 tior_4 (channel 4) .............................................................................................142 table 8.27 tior_5 (channel 5) .............................................................................................143 table 8.28 register combinations in buffer operation..........................................................158 table 8.29 cascaded combinations........................................................................................161 table 8.30 pwm output registers and output pins...............................................................163 table 8.31 phase counting mode clock input pins ...............................................................167 table 8.32 up/down-count conditions in phase counting mode 1......................................168 table 8.33 up/down-count conditions in phase counting mode 2......................................169 table 8.34 up/down-count conditions in phase counting mode 3......................................170 table 8.35 up/down-count conditions in phase counting mode 4......................................171 table 8.36 tpu interrupts ......................................................................................................1 74 section 9 watchdog timer (wdt) table 9.1 wdt interrupt sources.............................................................................................200 section 10 serial communication interface (sci) table 10.1 pin configuration..................................................................................................20 5 table 10.2 relationships between n setting in brr and bit rate b .....................................218 table 10.3 brr settings for various bit rates (asynchronous mode) (1) ...........................219 table 10.3 brr settings for various bit rates (asynchronous mode) (2) ...........................220 table 10.3 brr settings for various bit rates (asynchronous mode) (3) ...........................221 table 10.4 maximum bit rate for each frequency (asynchronous mode)...........................221 table 10.5 maximum bit rate with external clock input (asynchronous mode).................222 table 10.6 brr settings for various bit rates (clocked synchronous mode) .....................223 table 10.7 maximum bit rate with external clock input (clocked synchronous mode).....223 table 10.8 examples of bit rate for various brr settings (smart card interface mode) (when n = 0 and s = 372).....................................................................................224 table 10.9 maximum bit rate at various frequencies (smart card interface mode) (when s = 372)......................................................................................................224 table 10.10 serial transfer formats (asynchronous mode)....................................................226 table 10.11 ssr status flags and receive data handling ......................................................233 rev. 0.5, 03/03, page xxvi of xxvi table 10.12 sci interrupt sources............................................................................................ 261 table 10.13 sci interrupt sources............................................................................................ 262 section 11 hitachi controller area network (hcan) table 11.1 pin configuration.................................................................................................. 26 7 table 11.2 limits for settable value ...................................................................................... 296 table 11.3 setting range for tseg1 and tseg2 in bcr..................................................... 297 table 11.4 hcan interrupt sources....................................................................................... 308 section 12 a/d converter table 12.1 pin configuration.................................................................................................. 31 3 table 12.2 analog input channels and corresponding addr registers .............................. 314 table 12.3 a/d conversion time (single mode)................................................................... 320 table 12.4 a/d conversion time (scan mode) ..................................................................... 320 table 12.5 a/d converter interrupt source............................................................................ 321 table 12.6 analog pin specifications..................................................................................... 326 section 14 rom table 14.1 differences between boot mode and user program mode .................................. 331 table 14.2 pin configuration.................................................................................................. 33 5 table 14.3 setting on-board programming modes................................................................ 339 table 14.4 boot mode operation ........................................................................................... 341 table 14.5 system clock frequencies for which automatic adjustment of lsi bit rate is possible .................................................................................... 341 table 14.6 flash memory operating states............................................................................ 350 section 15 clock pulse generator table 15.1 damping resistance value ................................................................................... 354 table 15.2 crystal resonator characteristics ......................................................................... 355 table 15.3 external clock input conditions........................................................................... 356 section 16 power-down modes table 16.1 power-down mode transition conditions ........................................................... 363 table 16.2 lsi internal states in each mode ......................................................................... 364 table 16.3 oscillation stabilization time settings................................................................. 373 table 16.4 pin state in each processing state..................................................................... 389 section 18 electrical characteristics table 18.1 absolute maximum ratings ................................................................................. 417 table 18.2 dc characteristics ................................................................................................ 418 table 18.3 permissible output currents ................................................................................. 420 table 18.4 clock timing ........................................................................................................ 4 21 table 18.5 control signal timing .......................................................................................... 422 table 18.6 timing of on-chip peripheral modules ............................................................... 424 table 18.7 a/d conversion characteristics............................................................................ 427 table 18.8 flash memory characteristics .............................................................................. 428 rev. 0.5, 03/03, page 1 of 438 section 1 overview 1.1 features ? high-speed h8s/2600 central processing unit with an internal 16-bit architecture upward-compatible with h8/300 and h8/300h cpus on an object level sixteen 16-bit general registers 69 basic instructions ? various peripheral functions 16-bit timer pulse unit (tpu) watchdog timer asynchronous or clocked synchronous serial communication interface (sci) hitachi controller area network (hcan) 10-bit a/d converter clock pulse generator ? on-chip memory rom model rom ram remarks f-ztat version HD64F2615 64 kbytes 4 kbytes masked rom version hd6432615 64 kbytes 4 kbytes in planning ? general i/o ports i/o pins: 39 input-only pins: 17 ? supports various power-down modes ? compact package package code body size pin pitch qfp-80q fp-80q 14.0 14.0 mm 0.65 mm rev. 0.5, 03/03, page 2 of 438 1.2 internal block diagram internal data bus peripheral data bus peripheral address bus pd7 pd6 pd5 pd4 vcl vcl vcc v cc v cc v ss v ss v ss pa3/sck2 pa2/rxd2 pa1/txd2 pa0 pb7/tiocb5 pb6/tioca5 pb5/tiocb4 pb4/tioca4 pb3/tiocd3 pb2/tiocc3 pb1/tiocb3 pb0/tioca3 pc7 pc6 pc5/sck1/ pc4/rxd1 pc3/txd1 pc2/sck0/ pc1/rxd0 pc0/txd0 p97 / an15 p96 / an14 p95 / an13 p94 / an12 p93 / an11 p92 / an10 p91 / an9 p90 / an8 hrxd htxd avcc avss p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 pf7/ pf6 pf5 pf4 pf3/ / pf2 pf1 pf0/ rom (mask rom, flash memory) ram wdt 2 channels tpu 6 channels sci 3 channels hcan 1 channel a/d converter md2 md1 md0 extal xtal pllvcl pllcap pllvss fwe/nc * nmi h8s/2600 cpu interrupt controller port 9 port 4 internal address bus note: * the fwe pin is available only in the flash memory version. the nc pin is available only in the masked rom version. p17/tiocb2/tclkd p16/tioca2/ p15/tiocb1/tclkc p14/tioca1/ p13/tiocd0/tclkb p12/tiocc0/tclka p11/tiocb0 p10/tioca0 port 1 port f port d port c port b bus controller port a pll clock pulse generator figure 1.1 internal block diagram rev. 0.5, 03/03, page 3 of 438 1.3 pin arrangement md2 md1 md0 pa3/sck2 pa2/rxd2 pa1/txd2 pa 0 pb7/tiocb5 pb6/tioca5 pb5/tiocb4 pb4/tioca4 pb3/tiocd3 pb2/tiocc3 vcc pb1/tiocb3 vss pb0/tioca3 pc7 pc6 pc5/sck1/ avcc p93/an11 p92/an10 p91/an9 p90/an8 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 avss p10/tioca0 vcc p11/tiocb0 vss p12/tiocc0/tclka vcl p13/tiocd0/tclkb p14/tioca1/ p15/tiocb1/tclkc p16/tioca2/ p17/tiocb2/tclkd htxd hrxd pf0/ pf1 pf2 pf3/ / pf4 pf5 pf6 pf7/ pc0/txd0 pc1/rxd0 pc2/sck0/ pc3/txd1 pc4/rxd1 p94/an12 p95/an13 p96/an14 p97/an15 pd4 pd5 pd6 pd7 vcl fwe/nc * vss extal vcc xtal pllvss pllvcl nmi pllcap top view (fp-80q) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 note : * the fwe pin is available only in the flash memory version. the nc pin is available only in the masked rom version. figure 1.2 pin arrangement rev. 0.5, 03/03, page 4 of 438 1.4 pin functions type symbol pin no. i/o function power supply vcc 27 48 76 input power supply pins. connect all these pins to the system power supply. vss 25 50 78 input ground pins. connect all these pins to the system power supply (0 v). vcl 52 80 output external capacitance pin for internal step-down power supply. connect these pins to vss via a 0.1-f capacitor (placed close to the pins). clock pllvcl 44 output external capacitance pin for internal step-down power supply for an on-chip pll oscillator. connect this pin to pllvss via a 0.1-f capacitor (placed close to the pins). pllvss 46 input on-chip pll oscillator ground pin. pllcap 42 output external capacitance pin for an on-chip pll oscillator. xtal 47 input for connection to a crystal resonator. for examples of crystal resonator connection and external clock input, see section 15, clock pulse generator. extal 49 input for connection to a crystal resonator. an external clock can be input to the extal pin. for examples of crystal resonator connection and external clock input, see section 15, clock pulse generator. 15 output supplies the system clock to external devices. operating mode control md2 md1 md0 40 39 38 input set the operating mode. inputs at these pins should not be changed during operation. system control res 41 input reset input pin. when this pin is low, the chip is reset. stby 45 input when this pin is low, a transition is made to hardware standby mode. fwe 51 input pin for use by flash memory. this pin is only available in the flash memory version. rev. 0.5, 03/03, page 5 of 438 type symbol pin no. i/o function interrupts nmi 43 input nonmaskable interrupt request pin. if this pin is not used, it should be fixed high. irq5 irq4 irq3 irq2 irq1 irq0 21 18 11 8 4 2 input these pins request a maskable interrupt. 16-bit timer pulse unit tclka tclkb tclkc tclkd 79 1 3 5 input these pins input an external clock. tioca0 tiocb0 tiocc0 tiocd0 75 77 79 1 input/ output tgra_0 to tgrd_0 input capture input/output compare output/pwm output pins. tioca1 tiocb1 2 3 input/ output tgra_1 and tgrb_1 input capture input/output compare output/pwm output pins. tioca2 tiocb2 4 5 input/ output tgra_2 and tgrb_2 input capture input/output compare output/pwm output pins. tioca3 tiocb3 tiocc3 tiocd3 24 26 28 29 input/ output tgra_3 to tgrd_3 input capture input/output compare output/pwm output pins. tioca4 tiocb4 30 31 input/ output tgra_4 and tgrb_4 input capture input/output compare output/pwm output pins. tioca5 tiocb5 32 33 input/ output tgra_5 and tgrb_5 input capture input/output compare output/pwm output pins. txd2 txd1 txd0 35 19 16 output data output pins rxd2 rxd1 rxd0 36 20 17 input data input pins serial communi- cation interface (sci)/ smart card interface sck2 sck1 sck0 37 21 18 input/ output clock input/output pins hcan htxd 6 output can bus transmission pin hrxd 7 input can bus reception pin rev. 0.5, 03/03, page 6 of 438 type symbol pin no. i/o function a/d converter an15 an14 an13 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 57 58 59 60 62 63 64 65 66 67 68 69 70 71 72 73 input analog input pins adtrg 11 input pin for input of an external trigger to start a/d conversion avcc 61 input power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+5 v). avss 74 input the ground pin for the a/d converter. connect this pin to the system power supply (0 v). i/o ports p17 p16 p15 p14 p13 p12 p11 p10 5 4 3 2 1 79 77 75 input/ output 8-bit input/output pins p47 p46 p45 p44 p43 p42 p41 p40 66 67 68 69 70 71 72 73 input 8-bit input pins rev. 0.5, 03/03, page 7 of 438 type symbol pin no. i/o function i/o ports p97 p96 p95 p94 p93 p92 p91 p90 57 58 59 60 62 63 64 65 input 8-bit input pins pa3 pa2 pa1 pa0 37 36 35 34 input/ output 4-bit input/output pins pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 33 32 31 30 29 28 26 24 input/ output 8-bit input/output pins pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 23 22 21 20 19 18 17 16 input/ output 8-bit input/output pins pd7 pd6 pd5 pd4 53 54 55 56 input/ output 4-bit input/output pins pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 15 14 13 12 11 10 9 8 input/ output 8-bit input/output pins rev. 0.5, 03/03, page 8 of 438 rev. 0.5, 03/03, page 9 of 438 section 2 cpu the h8s/2600 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2600 cpu has sixteen 16-bit general registers, can address a 16-mbyte linear address space, and is ideal for realtime control. this section describes the h8s/2600 cpu. the usable modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. 2.1 features ? upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h cpus object programs ? general-register architecture ? sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers ? sixty-nine basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? multiply-and-accumulate instruction ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes ? high-speed operation ? all frequently-used instructions execute in one or two states ? 8/16/32-bit register-register add/subtract : 1 state ? 8 8-bit register-register multiply : 3 states ? 16 8-bit register-register divide : 12 states ? 16 16-bit register-register multiply : 4 states ? 32 16-bit register-register divide : 20 states rev. 0.5, 03/03, page 10 of 438 ? two cpu operating modes ? normal mode* ? advanced mode ? power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection note: * normal mode is not available in this lsi. 2.1.1 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are shown below. ? register configuration the mac register is supported by the h8s/2600 cpu only. ? basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported by the h8s/2600 cpu only. ? the number of execution states of the mulxu and mulxs instructions; execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 in addition, there are differences in address space, ccr and exr register functions, and power- down modes, etc., depending on the model. rev. 0.5, 03/03, page 11 of 438 2.1.2 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2600 cpu has the following enhancements: ? more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. ? expanded address space ? normal mode supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. ? enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? a multiply-and-accumulate instruction has been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. 2.1.3 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2600 cpu has the following enhancements: ? additional control register ? one 8-bit and two 32-bit control registers have been added. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? a multiply-and-accumulate instruction has been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. rev. 0.5, 03/03, page 12 of 438 2.2 cpu operating modes the h8s/2600 cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space. the mode is selected by the mode pins. 2.2.1 normal mode the exception vector table and stack have the same structure as in the h8/300 cpu. ? address space a maximum address space of 64 kbytes can be accessed. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@?rn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected. ? instruction set all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. ? exception vector table and memory indirect branch addresses in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits. the exception vector table differs depending on the microcontroller. for details on the exception vector table, see section 4, exception handling. the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. ? stack structure when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. exr is not pushed onto the stack in interrupt control mode 0. for details, see section 4, exception handling. note: normal mode is not available in this lsi. rev. 0.5, 03/03, page 13 of 438 h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector (reserved for system use) (reserved for system use) exception vector 1 exception vector 2 exception vector table figure 2.1 exception vector table (normal mode) pc (16 bits) exr * 1 reserved * 1 * 3 ccr ccr * 3 pc (16 bits) sp sp (sp * 2 1. when exr is not used it is not stored on the stack. 2. sp when exr is not used. 3. lgnored when returning. notes: (b) exception handling (a) subroutine branch ) figure 2.2 stack structure in normal mode 2.2.2 advanced mode ? address space linear access is provided to a 16-mbyte maximum address space is provided. ? extended registers (en) the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. ? instruction set all instructions and addressing modes can be used. rev. 0.5, 03/03, page 14 of 438 ? exception vector table and memory indirect branch addresses in advanced mode, the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). for details on the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c h'00000010 h'00000008 h'00000007 reserved reserved reserved reserved reserved exception vector 1 exception vector 2 exception vector 3 exception vector 4 exception vector table exception vector 5 figure 2.3 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. ? stack structure in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. rev. 0.5, 03/03, page 15 of 438 pc (24 bits) exr * 1 reserved * 1 * 3 ccr pc (24 bits) sp sp (sp * 2 reserved (a) subroutine branch (b) exception handling notes: 1. when exr is not used it is not stored on the stack. 2. sp when exr is not used. 3. ignored when returning. ) figure 2.4 stack structure in advanced mode rev. 0.5, 03/03, page 16 of 438 2.3 address space figure 2.5 shows a memory map for the h8s/2600 cpu. the h8s/2600 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. the usable modes and address spaces differ depending on the product. for details on each product, refer to section 3, mcu operating modes. h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff 64-kbyte 16-mbyte cannot be used in this lsi program area data area (b) advanced mode (a) normal mode figure 2.5 memory map rev. 0.5, 03/03, page 17 of 438 2.4 register configuration the h8s/2600 cpu has the internal registers shown in figure 2.6. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), an 8-bit extended control register (exr), an 8-bit condition code register (ccr), and a 64-bit multiply-accumulate register (mac). t i2i1i0 exr 76543210 pc mach macl mac 23 63 32 41 31 0 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp pc exr t i2 to i0 ccr i ui :stack pointer :program counter :extended control register :trace bit :interrupt mask bits :condition-code register :interrupt mask bit :user bit or interrupt mask bit :half-carry flag :user bit :negative flag :zero flag :overflow flag :carry flag :multiply-accumulate register er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h u n z v c mac general registers (rn) and extended registers (en) control registers (cr) legend sign extension ---- figure 2.6 cpu registers rev. 0.5, 03/03, page 18 of 438 2.4.1 general registers the h8s/2600 cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. figure 2.7 illustrates the usage of the general registers. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8- bit registers. the usage of each register can be selected independently. general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.8 shows the stack. ? address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.7 usage of general registers rev. 0.5, 03/03, page 19 of 438 sp (er7) free area stack area figure 2.8 stack 2.4.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). 2.4.3 extended control register (exr) exr is an 8-bit register that manipulates the ldc, stc, andc, orc, and xorc instructions. when these instructions, except for the stc instruction, are executed, all interrupts including nmi will be masked for three states after execution is completed. bit bit name initial value r/w description 7 t 0 r/w trace bit when this bit is set to 1, a trace exception is generated each time an instruction is executed. when this bit is cleared to 0, instructions are executed in sequence. 6 to 3 ? all 1 ? reserved these bits are always read as 1. 2 1 0 i2 i1 i0 1 1 1 r/w r/w r/w these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. rev. 0.5, 03/03, page 20 of 438 2.4.4 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 by hardware at the start of an exception-handling sequence. for details, refer to section 5, interrupt controller. 6 ui undefined r/w user bit or interrupt mask bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit cannot be used as an interrupt mask bit in this lsi. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. rev. 0.5, 03/03, page 21 of 438 bit bit name initial value r/w description 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 multiply-accumulate register (mac) this 64-bit register stores the results of multiply-and-accumulate operations. it consists of two 32- bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are a sign extension. 2.4.6 initial values of cpu registers reset exception handling loads the cpu's program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. rev. 0.5, 03/03, page 22 of 438 2.5 data formats the h8s/2600 cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.9 shows the data formats in general registers. 70 70 msb lsb msb lsb 70 43 don't care don't care don't care 70 43 70 don't care 65432 710 70 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type register number data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.9 general register data formats (1) rev. 0.5, 03/03, page 23 of 438 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb en rn ern en rn rnh rnl msb lsb : general register er : general register e : general register r : general register rh : general register rl : most significant bit : least significant bit data type data format register number word data word data rn en longword data legend ern figure 2.9 general register data formats (2) rev. 0.5, 03/03, page 24 of 438 2.5.2 memory data formats figure 2.10 shows the data formats in memory. the h8s/2600 cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 is used as an address register to access the stack, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.10 memory data formats rev. 0.5, 03/03, page 25 of 438 2.6 instruction set the h8s/2600 cpu has 69 instructions. the instructions are classified by function in table 2.1. table 2.1 instruction classification function instructions size types data transfer mov b/w/l 5 pop * 1 , push * 1 w/l ldm, stm l movfpe * 3 , movtpe * 3 b arithmetic add, sub, cmp, neg b/w/l 23 operations addx, subx, daa, das b inc, dec b/w/l adds, subs l mulxu, divxu, mulxs, divxs b/w extu, exts w/l tas * 4 b mac, ldmac, stmac, clrmac ? logic operations and, or, xor, not b/w/l 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr b/w/l 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 total: 69 notes: b-byte; w-word; l-longword. 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @-sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in this lsi. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. rev. 0.5, 03/03, page 26 of 438 2.6.1 table of instructions classified by function tables 2.3 to 2.10 summarize the instructions in each functional category. the notation used in tables 2.3 to 2.10 is defined below. table 2.2 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). rev. 0.5, 03/03, page 27 of 438 table 2.3 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in this lsi. movtpe b cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. ldm l @sp+ rn (register list) pops two or more general registers from the stack. stm l rn (register list) @?sp pushes two or more general registers onto the stack. note: * refers to the operand size. b: byte w: word l: longword rev. 0.5, 03/03, page 28 of 438 table 2.4 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword rev. 0.5, 03/03, page 29 of 438 table 2.4 arithmetic operations instructions (2) instruction size * 1 function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas * 2 b @erd ? 0, 1 ( rev. 0.5, 03/03, page 30 of 438 table 2.5 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.6 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. rotl rotr b/w/l rd (rotate) rd rotates general register contents. 1-bit or 2-bit rotations are possible. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. note: * refers to the operand size. b: byte w: word l: longword rev. 0.5, 03/03, page 31 of 438 table 2.7 bit manipulation instructions (1) instruction size * function bset b 1 ( rev. 0.5, 03/03, page 32 of 438 table 2.7 bit manipulation instructions (2) instruction size * 1 function bxor bixor b b c ( rev. 0.5, 03/03, page 33 of 438 table 2.8 branch instructions instruction size function bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine rev. 0.5, 03/03, page 34 of 438 table 2.9 system control instructions instruction size * function trapa ? starts trap-instruction exception handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr, (eas) exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically xors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word l: longword rev. 0.5, 03/03, page 35 of 438 table 2.10 block data transfer instructions instruction size function eepmov.b eepmov.w ? ? if r4l 0 then repeat @er5+ @er6+ r4l?1 r4l until r4l = 0 else next; if r4 0 then repeat @er5+ @er6+ r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction begins as soon as the transfer is completed. 2.6.2 basic instruction formats this lsi instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). figure 2.11 shows examples of instruction formats. rev. 0.5, 03/03, page 36 of 438 ? operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. ? condition field specifies the branching condition of bcc instructions. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. rn rm op ea(disp) op cc ea(disp) bra d:16, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.11 instruction formats (examples) rev. 0.5, 03/03, page 37 of 438 2.7 addressing modes and effective address calculation the h8s/2600 cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program- counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 2.7.1 register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2.7.2 register indirect?@ern the register field of the instruction code specifies an address register (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). 2.7.3 register indirect with displacement?@(d:16, ern) or @(d:32, ern) a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. rev. 0.5, 03/03, page 38 of 438 2.7.4 register indirect with post-increment or pre-decrement?@ern+ or @-ern register indirect with post-increment?@ern+: the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for the word or longword transfer instructions, the register value should be even. register indirect with pre-decrement?@-ern: the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result is the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for the word or longword transfer instructions, the register value should be even. 2.7.5 absolute address?@aa:8, @aa:16, @aa:24, or @aa:32 the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). table 2.12 indicates the accessible absolute address ranges. to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.12 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: normal mode is not available in this lsi. rev. 0.5, 03/03, page 39 of 438 2.7.6 immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. 2.7.8 memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode, the memory operand is a word operand and the branch address is 16 bits long. in advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) note: normal mode is not available in this lsi. rev. 0.5, 03/03, page 40 of 438 specified by @aa:8 specified by @aa:8 branch address branch address reserved (a) normal mode * (a) advanced mode note: * normal mode is not available in this lsi. figure 2.12 branch address specification in memory indirect mode 2.7.9 effective address calculation table 2.13 indicates how effective addresses are calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. note: normal mode is not available in this lsi. rev. 0.5, 03/03, page 41 of 438 table 2.13 effective address calculation (1) no 1 offset 1 2 4 r op 31 0 31 23 2 3 register indirect with displacement @(d:16,ern) or @(d:32,ern) 4 r op disp r op rm op rn 31 0 31 0 r op don't care 31 23 31 0 don't care 31 0 disp 31 0 31 0 31 23 31 0 don't care 31 23 31 0 don't care 24 24 24 24 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand size byte word longword operand is general register contents. rev. 0.5, 03/03, page 42 of 438 table 2.13 effective address calculation (2) no 5 op 31 23 31 0 don't care abs @aa:8 7 h'ffff op 31 23 31 0 don't care @aa:16 op @aa:24 @aa:32 abs 15 16 31 23 31 0 don't care 31 23 31 0 don't care abs op abs 6 op imm #xx:8/#xx:16/#xx:32 8 24 24 24 24 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 31 23 7 program-counter relative @ (d:8,pc) @(d:16,pc) memory indirect @@ aa:8 normal mode* advanced mode 31 0 don't care 23 0 disp 0 31 23 31 0 don't care disp op 23 op 8 abs 31 0 abs h'000000 7 8 0 15 31 23 31 0 don't care 15 h'00 16 op abs 31 0 abs h'000000 7 8 0 31 24 24 24 note: * normal mode is not available in this lsi. pc contents sign extension memory contents memory contents rev. 0.5, 03/03, page 43 of 438 2.8 processing states the h8s/2600 cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2.14 shows a diagram of the processing states. figure 2.13 indicates the state transitions. ? reset state in this state, the cpu and all on-chip peripheral modules are initialized and not operating. when the res input goes low, all current processing stops and the cpu enters the reset state. all interrupts are masked in the reset state. reset exception handling starts when the res signal changes from low to high. for details, refer to section 4, exception handling. the reset state can also be entered by a watchdog timer overflow. ? exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. for further details, refer to section 4, exception handling. ? program execution state in this state, the cpu executes program instructions in sequence. ? bus-released state in a product which has a bus master other than the cpu, such as a data transfer controller (dtc), the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. ? program stop state this is a power-down state in which the cpu stops operating. the program stop state occurs when a sleep instruction is executed or the cpu enters hardware standby mode. for further details, refer to section 16, power-down modes. rev. 0.5, 03/03, page 44 of 438 program execution state exception handling state program halt state bus-released state reset state * end of bus request bus request interrupt request sleep instruction = high = h igh, = low notes: from any state, a transition to hardware standby mode occurs when goes low. * from any state except hardware standby mode, a transition to the reset state occurs whenever goes low. a transition can also be made to the reset state when the watchdog timer overflows. bus request end of bus request request for exception handling end of exception handling figure 2.13 state transitions 2.9 usage notes 2.9.1 usage notes on bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions are used to read data in bytes, then, after bit manipulation, they write data in bytes again. therefore, special care is necessary to use these instructions for the registers and the ports that include write-only bit. the bclr instruction can be used to clear the flags in the internal i/o registers to 0. in this time, if it is obvious that the flag has been set to 1 in the interrupt processing routine or other processing, there is no need to read the flag beforehand. rev. 0.5, 03/03, page 45 of 438 section 3 mcu operating modes 3.1 operating mode selection this lsi supports only operating mode 7, that is, the advanced single-chip mode. the operating mode is determined by the setting of the mode pins (md2 to md0). only mode 7 can be used in this lsi. therefore, all mode pins must be fixed high, as shown in table 3.1. do not change the mode pin settings during operation. table 3.1 mcu operating mode selection external data bus mcu operating mode md2 md1 md0 cpu operating mode description on-chip rom initial width max. width 7 111advanced mode single-chip mode enabled ? ? rev. 0.5, 03/03, page 46 of 438 3.2 register descriptions the following registers are related to the operating mode. ? mode control register (mdcr) ? system control register (syscr) 3.2.1 mode control register (mdcr) mdcr monitors the current operating mode of this lsi. bit bit name initial value r/w descriptions 7 ? 1r/wreserved only 1 should be written to this bit. 6 to 3 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. 2 1 0 mds2 mds1 mds0 ? * ? * ? * r r r mode select 2 to 0 these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to md2 to md0. mds2 to mds0 are read- only bits and they cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. these latches are canceled by a reset. note: * the initial values are determined according to the settings of the md2 to md0 pins. 3.2.2 system control register (syscr) syscr selects saturating or non-saturating calculation for the mac instruction, selects the interrupt control mode and the detected edge for nmi, and enables or disables on-chip ram. bit bit name initial value r/w descriptions 7macs0 ? mac saturation selects either saturating or non-saturating calculation for the mac instruction. 0: non-saturating calculation for the mac instruction 1: saturating calculation for the mac instruction rev. 0.5, 03/03, page 47 of 438 bit bit name initial value r/w descriptions 6 ? 0 ? reserved this bit is always read as 0 and cannot be modified. 5 4 intm1 intm0 0 0 r/w r/w these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.6, interrupt control modes and interrupt operation. 00: interrupt control mode 0 01: setting prohibited 10: interrupt control mode 2 11: setting prohibited 3 nmieg 0 r/w nmi edge select selects the valid edge of the nmi interrupt input. 0: an interrupt is requested at the falling edge of nmi input 1: an interrupt is requested at the rising edge of nmi input 2 1 ? ? 0 0 ? ? reserved these bits are always read as 0 and cannot be modified. 0 rame 1 r/w ram enable enables or disables on-chip ram. the rame bit is initialized when the reset status is released. 0: on-chip ram is disabled 1: on-chip ram is enabled rev. 0.5, 03/03, page 48 of 438 3.3 pin functions in each operating mode the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, however external addresses cannot be accessed. all i/o ports are available for use as input/output ports. 3.3.1 pin functions table 3.2 shows their functions in mode 7. table 3.2 pin functions in each operating mode port mode 7 port 1 p10 p p11 to p13 p port a pa3 to pa0 p port b p port c p port d p port f pf7 p * /c pf6 to pf4 p pf3 pf2 to pf0 legend p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset rev. 0.5, 03/03, page 49 of 438 3.4 address map figure 3.1 shows the address map in each operating mode. h'000000 h'00ffff h'ffe000 h'ffefbf h'fff800 h'ffffc0 h'ffffff h'ffff3f h'ffff60 h'ffffbf on-chip rom (flash memory/ masked rom * ) on-chip ram on-chip ram internal i/o registers internal i/o registers rom: 64 kbytes, ram: 4 kbytes mode 7 advanced single-chip mode note : * in planning figure 3.1 address map rev. 0.5, 03/03, page 50 of 438 rev. 0.5, 03/03, page 51 of 438 section 4 exception handling 4.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. exception sources, the stack structure, and operation of the cpu vary depending on the interrupt control mode. for details on the interrupt control mode, refer to section 5, interrupt controller. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. the cpu enters the reset state when the res pin is low. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit in the exr is set to 1 direct transition starts when a direction transition occurs as the result of sleep instruction execution. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction * 3 started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in program execution state. 4.2 exception sources and exception vector table different vector addresses are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. since the usable modes differ depending on the product, for details on each product, refer to section 3, mcu operating modes. rev. 0.5, 03/03, page 52 of 438 table 4.2 exception handling vector table vector address * 1 exception source vector number normal mode advanced mode power-on reset 0 h'0000 to h'0001 h'0000 to h'0003 manual reset * 2 1 h'0002 to h'0003 h'0004 to h'0007 reserved for system use 2 h'0004 to h'0005 h'0008 to h'000b 3 h'0006 to h'0007 h'000c to h'000f 4 h'0008 to h'0019 h'0010 to h'0013 trace 5 h'000a to h'000b h'0014 to h'0017 interrupt (direct transitions) 6 h'000c to h'000d h'0018 to h'001b interrupt (nmi) 7 h'000e to h'000f h'001c to h'001f trap instruction (#0) 8 h'0010 to h'0011 h'0020 to h'0023 (#1) 9 h'0012 to h'0013 h'0024 to h'0027 (#2) 10 h'0014 to h'0015 h'0028 to h'002b (#3) 11 h'0016 to h'0017 h'002c to h'002f reserved for system use 12 h'0018 to h'0019 h'0030 to h'0033 13 h'001a to h'001b h'0034 to h'0037 14 h'001c to h'001d h'0038 to h'003b 15 h'001e to h'001f h'003c to h'003f external interrupt irq0 16 h'0020 to h'0021 h'0040 to h'0043 irq1 17 h'0022 to h'0023 h'0044 to h'0047 irq2 18 h'0024 to h'0025 h'0048 to h'004b irq3 19 h'0026 to h'0027 h'004c to h'004f irq4 20 h'0028 to h'0029 h'0050 to h'0053 irq5 21 h'002a to h'002b h'0054 to h'0057 reserved for system use 22 h'002c to h'002d h'0058 to h'005b 23 h'002e to h'002f h'005c to h'005f internal interrupt * 3 24 ? 127 h'0030 to h'0031 ? h'00fe to h'00ff h'0060 to h'0063 ? h'01fc to h'01ff notes: 1. lower 16 bits of the address. 2. not available in this lsi. 3. for details of internal interrupt vectors, see section 5.5, interrupt exception handling vector table. rev. 0.5, 03/03, page 53 of 438 4.3 reset a reset has the highest exception priority. when the res pin goes low, all processing halts and this lsi enters the reset. to ensure that this lsi is reset, hold the res pin low for at least 20 ms at power-up. to reset the chip during operation, hold the res pin low for at least 20 states. a reset initializes the internal state of the cpu and the registers of on-chip peripheral modules. the chip can also be reset by overflow of the watchdog timer. for details, see section 9, watchdog timer (wdt). the interrupt control mode is 0 immediately after reset. 4.3.1 reset exception handling when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4.1 and 4.2 show examples of the reset sequence. rev. 0.5, 03/03, page 54 of 438 high vector fetch internal processing prefetch of first program instruction (1)(3) reset exception handling vector address(when reset, (1)=h'000000, (3)=h'000002) (2)(4) start address (contents of reset exception handling vector address) (5) start address ((5)=(2)(4)) (6) first program instruction internal address bus internal read signal internal write signal internal data bus (1) (2) (4) (6) (3) (5) figure 4.1 reset sequence (advanced mode with on-chip rom enabled) rev. 0.5, 03/03, page 55 of 438 , d15 d0 high * * * address bus vector fetch internal processing prefetch of first program instruction (1) (2) (4) (6) (3) (5) (1)(3) reset exception handling vector address(when reset, (1)=h'000000, (3)=h'000002) (2)(4) start address (contents of reset exception handling vector address) (5) start address ((5)=(2)(4)) (6) first program instruction note: * three program wait states are inserted. figure 4.2 reset sequence (advanced mode with on-chip rom disabled: cannot be used in this lsi) 4.3.2 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 4.3.3 state of on-chip peripheral modules after reset release after reset release, mstpcra to mstpcrc are initialized to h'3f, h'ff, and h'ff, respectively, and all modules enter module stop mode. consequently, on-chip peripheral module registers cannot be read or written to. register reading and writing is enabled when the module stop mode is exited. rev. 0.5, 03/03, page 56 of 438 4.4 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trace mode, a trace exception occurs on completion of each instruction. trace mode is not affected by interrupt masking. table 4.3 shows the state of ccr and exr after execution of trace exception handling. trace mode is canceled by clearing the t bit in exr to 0. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. interrupts are accepted even within the trace exception handling routine. table 4.3 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 21??0 legend 1: set to 1 0: cleared to 0 ?: retains value prior to execution 4.5 interrupts interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. the source to start interrupt exception handling and the vector address differ depending on the product. for details, refer to section 5, interrupt controller. interrupt exception handling is conducted as follows: 1. the values in the program counter (pc), condition code register (ccr), and extended control register (exr) are saved to the stack. 2. the interrupt mask bit is updated and the t bit is cleared to 0. 3. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and program execution begins from that address. rev. 0.5, 03/03, page 57 of 438 4.6 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. trap instruction exception handling is conducted as follows: 1. the values in the program counter (pc), condition code register ( ccr), and extended control register (exr) are saved to the stack. 2. the interrupt mask bit is updated and the t bit is cleared. 3. a vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the pc, and program execution starts from that address. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4.4 shows the status of ccr and exr after execution of trap instruction exception handling. table 4.4 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 01??? 21??0 legend 1: set to 1 0: cleared to 0 ?: retains value prior to execution rev. 0.5, 03/03, page 58 of 438 4.7 stack status after exception handling figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. ccr ccr * 1 pc(16 bits) sp exr reserved * 1 ccr ccr * 1 pc(16 bits) sp ccr pc(24 bits) sp exr reserved * 1 ccr pc(24 bits) sp (a) normal modes * 2 (b) advanced modes interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 note: 1. 2. ignored on return. normal modes are not available in this lsi. figure 4.3 stack status after exception handling rev. 0.5, 03/03, page 59 of 438 4.8 usage note when accessing word data or longword data, this lsi assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.4 shows an example of what happens when the sp value is odd. sp ccr : pc : r1l : sp : condition code register program counter general register r1l stack pointer ccr sp sp r1l h'fffefa h'fffefb h'fffefc h'fffefd h'fffefe h'fffeff pc pc trapa instruction executed sp set to h'fffeff data saved above sp mov.b r1l, @-er7 executed contents of ccr lost address legend note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. figure 4.4 operation when sp value is odd rev. 0.5, 03/03, page 60 of 438 rev. 0.5, 03/03, page 61 of 438 section 5 interrupt controller 5.1 features ? two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? seven external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq0 to irq5. rev. 0.5, 03/03, page 62 of 438 a block diagram of the interrupt controller is shown in figure 5.1. syscr nmi input irq input internal interrupt request wovi0 to sle0 nmieg intm1, intm0 nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu iscr ier isr ipr syscr : irq sense control register : irq enable register : irq status register : interrupt priority register : system control register legend figure 5.1 block diagram of interrupt controller rev. 0.5, 03/03, page 63 of 438 5.2 input/output pins table 5.1 summarizes the pins of the interrupt controller. table 5.1 pin configuration name i/o function nmi input nonmaskable external interrupt rising or falling edge can be selected irq5 irq4 irq3 irq2 irq1 irq0 input input input input input input maskable external interrupts rising, falling, or both edges, or level sensing, can be selected 5.3 register descriptions the interrupt controller has the following registers. for details on the system control register (syscr), refer to section 3.2.2, system control register (syscr). ? system control register (syscr) ? irq sense control register h (iscrh) ? irq sense control register l (iscrl) ? irq enable register (ier) ? irq status register (isr) ? interrupt priority register a (ipra) ? interrupt priority register b (iprb) ? interrupt priority register d (iprd) ? interrupt priority register e (ipre) ? interrupt priority register f (iprf) ? interrupt priority register g (iprg) ? interrupt priority register h (iprh) ? interrupt priority register j (iprj) ? interrupt priority register k (iprk) ? interrupt priority register m (iprm) rev. 0.5, 03/03, page 64 of 438 5.3.1 interrupt priority registers a, b, d to h, j, k, m (ipra, iprb, iprd to iprh, iprj, iprk, iprm) ipr are ten 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between interrupt sources and ipr settings is shown in table 5.2 (interrupt sources, vector addresses, and interrupt priorities). setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt. bit bit name initial value r/w description 7 ? 0 ? reserved these bits are always read as 0. 6 5 4 ipr6 ipr5 ipr4 1 1 1 r/w r/w r/w sets the priority of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) 3 ? 0 ? reserved these bits are always read as 0. 2 1 0 ipr2 ipr1 ipr0 1 1 1 r/w r/w r/w sets the priority of the corresponding interrupt source. 000: priority level 0 (lowest) 001: priority level 1 010: priority level 2 011: priority level 3 100: priority level 4 101: priority level 5 110: priority level 6 111: priority level 7 (highest) rev. 0.5, 03/03, page 65 of 438 5.3.2 irq enable register (ier) ier controls the enabling and disabling of interrupt requests irq0 to irq5. bit bit name initial value r/w description 7 6 ? ? 0 0 r/w r/w reserved only 0 should be written to these bits. 5 irq5e 0 r/w irq5 enable the irq5 interrupt request is enabled when this bit is 1. 4 irq4e 0 r/w irq4 enable the irq4 interrupt request is enabled when this bit is 1. 3 irq3e 0 r/w irq3 enable the irq3 interrupt request is enabled when this bit is 1. 2 irq2e 0 r/w irq2 enable the irq2 interrupt request is enabled when this bit is 1. 1 irq1e 0 r/w irq1 enable the irq1 interrupt request is enabled when this bit is 1. 0 irq0e 0 r/w irq0 enable the irq0 interrupt request is enabled when this bit is 1. rev. 0.5, 03/03, page 66 of 438 5.3.3 irq sense control registers h and l (iscrh, iscrl) iscr selects the source that generates an interrupt request at pins irq0 to irq5 . bit bit name initial value r/w description 15 to 12 ? all 0 r/w reserved only 0 should be written to these bits. 11 10 irq5scb irq5sca 0 0 r/w r/w irq5 sense control b irq5 sense control a 00: interrupt request generated at irq5 input level low 01: interrupt request generated at falling edge of irq5 input 10: interrupt request generated at rising edge of irq5 input 11: interrupt request generated at both falling and rising edges of irq5 input 9 8 irq4scb irq4sca 0 0 r/w r/w irq4 sense control b irq4 sense control a 00: interrupt request generated at irq4 input level low 01: interrupt request generated at falling edge of irq4 input 10: interrupt request generated at rising edge of irq4 input 11: interrupt request generated at both falling and rising edges of irq4 input 7 6 irq3scb irq3sca 0 0 r/w r/w irq3 sense control b irq3 sense control a 00: interrupt request generated at irq3 input level low 01: interrupt request generated at falling edge of irq3 input 10: interrupt request generated at rising edge of irq3 input 11: interrupt request generated at both falling and rising edges of irq3 input rev. 0.5, 03/03, page 67 of 438 bit bit name initial value r/w description 5 4 irq2scb irq2sca 0 0 r/w r/w irq2 sense control b irq2 sense control a 00: interrupt request generated at irq2 input level low 01: interrupt request generated at falling edge of irq2 input 10: interrupt request generated at rising edge of irq2 input 11: interrupt request generated at both falling and rising edges of irq2 input 3 2 irq1scb irq1sca 0 0 r/w r/w irq1 sense control b irq1 sense control a 00: interrupt request generated at irq1 input level low 01: interrupt request generated at falling edge of irq1 input 10: interrupt request generated at rising edge of irq1 input 11: interrupt request generated at both falling and rising edges of irq1 input 1 0 irq0scb irq0sca 0 0 r/w r/w irq0 sense control b irq0 sense control a 00: interrupt request generated at irq0 input level low 01: interrupt request generated at falling edge of irq0 input 10: interrupt request generated at rising edge of irq0 input 11: interrupt request generated at both falling and rising edges of irq0 input rev. 0.5, 03/03, page 68 of 438 5.3.4 irq status register (isr) isr indicates the status of irq0 to irq5 interrupt requests. bit bit name initial value r/w description 7 6 ? ? 0 0 r/w r/w reserved only 0 should be written to these bits. 5 4 3 2 1 0 irq5f irq4f irq3f irq2f irq1f irq0f 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w [setting conditions] when the interrupt source selected by the iscr registers occurs [clearing conditions] ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set (n=5 to 0) 5.4 interrupt 5.4.1 external interrupts there are seven external interrupts: nmi and irq0 to irq5. these interrupts can be used to restore this lsi from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. irq0 to irq5 interrupts: interrupts irq0 to irq5 are requested by an input signal at pins irq0 to irq5 . interrupts irq0 to irq5 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq0 to irq5 . ? enabling or disabling of interrupt requests irq0 to irq5 can be selected with ier. ? the interrupt priority level can be set with ipr. rev. 0.5, 03/03, page 69 of 438 ? the status of interrupt requests irq0 to irq5 is indicated in isr. isr flags can be cleared to 0 by software. the detection of irq0 to irq5 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0; and use the pin as an i/o pin for another function. a block diagram of interrupts irq0 to irq5 is shown in figure 5.2. irqn interrupt request irqne irqnf s r q clear signal edge / level detection circuit irqnsca, irqnscb input note: n= 5 to 0 figure 5.2 block diagram of interrupts irq0 to irq5 5.4.2 internal interrupts the sources for internal interrupts from on-chip peripheral modules have the following features: ? for each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. ? the interrupt priority level can be set by means of ipr. 5.5 interrupt exception handling vector table table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of the ipr. modules set at the same priority will conform to their default priorities. priorities within a module are fixed. rev. 0.5, 03/03, page 70 of 438 table 5.2 interrupt sources, vector addresses, and interrupt priorities vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority external pin nmi 7 h'001c high irq0 16 h'0040 ipra6 to ipra4 irq1 17 h'0044 ipra2 to ipra0 irq2 18 h'0048 iprb6 to iprb4 irq3 19 h'004c irq4 20 h'0050 iprb2 to iprb0 irq5 21 h'0054 ? reserved for system use 22 h'0058 reserved for system use 23 h'005c watchdog timer 0 wovi0 25 h'0064 iprd6 to iprd4 a/d adi 28 h'0070 ipre2 to ipre0 watchdog timer 1 wovi1 29 h'0074 ipre2 to ipre0 tgi0a 32 h'0080 iprf6 to iprf4 tpu channel 0 tgi0b 33 h'0084 tgi0c 34 h'0088 tgi0d 35 h'008c tci0v 36 h'0090 tgi1a 40 h'00a0 iprf2 to iprf0 tpu channel 1 tgi1b 41 h'00a4 tci1v 42 h'00a8 tci1u 43 h'00ac tgi2a 44 h'00b0 iprg6 to iprg4 tpu channel 2 tgi2b 45 h'00b4 tci2v 46 h'00b8 tci2u 47 h'00bc low rev. 0.5, 03/03, page 71 of 438 vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority tgi3a 48 h'00c0 iprg2 to iprg0 high tpu channel 3 tgi3b 49 h'00c4 tgi3c 50 h'00c8 tgi3d 51 h'00cc tci3v 52 h'00d0 tgi4a 56 h'00e0 iprh6 to iprh4 tpu channel 4 tgi4b 57 h'00e4 tci4v 58 h'00e8 tci4u 59 h'00ec tgi5a 60 h'00f0 iprh2 to iprh0 tpu channel 5 tgi5b 61 h'00f4 tci5v 62 h'00f8 tci5u 63 h'00fc eri0 80 h'0140 iprj2 to iprj0 sci channel 0 rxi0 81 h'0144 txi0 82 h'0148 tei0 83 h'014c eri1 84 h'0150 iprk6 to iprk4 sci channel 1 rxi1 85 h'0154 txi1 86 h'0158 tei1 87 h'015c eri2 88 h'0160 iprk2 to iprk0 sci channel 2 rxi2 89 h'0164 txi2 90 h'0168 tei2 91 h'016c hcan ers0, ovr0 104 h'01a0 iprm6 to iprm4 rm0 105 h'01a4 rm1 106 h'01a8 sle0 107 h'01ac ? reserved for system use 111 h'01bc iprm2 to iprm0 low note: * lower 16 bits of the start address. rev. 0.5, 03/03, page 72 of 438 5.6 interrupt control modes and interrupt operation the interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. interrupt operations differ depending on the interrupt control mode. the interrupt control mode is selected by syscr. table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. table 5.3 interrupt control modes interrupt control mode priority setting registers interrupt mask bits description 0 default i the priorities of interrupt sources are fixed at the default settings. interrupt sources, except for nmi, are masked by the i bit. 2 ipr i2 to i0 8 priority levels other than nmi can be set with ipr. 8-level interrupt mask control is performed by bits i2 to i0. 5.6.1 interrupt control mode 0 in interrupt control mode 0, interrupt requests other than for nmi are masked by the i bit of the ccr in the cpu. figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. if the i bit is cleared, an interrupt request is accepted. 3. interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4. when the cpu accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this masks all interrupts except nmi. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. rev. 0.5, 03/03, page 73 of 438 program execution status interrupt generated? nmi irq0 irq1 sle0 i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no hold pending figure 5.3 flowchart of procedure up to interrupt acceptance in interrupt control mode 0 rev. 0.5, 03/03, page 74 of 438 5.6.2 interrupt control mode 2 in interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than nmi by comparing the exr interrupt mask level (i2 to i0 bits) in the cpu and the ipr setting. figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. when the cpu accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. 7. the cpu generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. rev. 0.5, 03/03, page 75 of 438 yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5.4 flowchart of procedure up to interrupt acceptance in control mode 2 5.6.3 interrupt exception handling sequence figure 5.5 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. rev. 0.5, 03/03, page 76 of 438 (14) (12) (10) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10)(12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) (8) figure 5.5 interrupt exception handling rev. 0.5, 03/03, page 77 of 438 5.6.4 interrupt response times table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5.4 are explained in table 5.5. this lsi is capable of fast word transfer to on-chip memory, has the program area in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 5.4 interrupt response times normal mode * 5 advanced mode no. execution status interrupt control mode 0 interrupt control mode 2 interrupt control mode 0 interrupt control mode 2 1 interrupt priority determination * 1 33 33 2 number of wait states until executing instruction ends * 2 1 to 19 +2s i 1 to 19+2s i 1 to 19+2s i 1 to 19+2s i 3 pc, ccr, exr stack save 2s k 3s k 2s k 3s k 4 vector fetch s i s i 2s i 2s i 5 instruction fetch * 3 2s i 2s i 2s i 2s i 6 internal processing * 4 22 22 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. 5. not available in this lsi. rev. 0.5, 03/03, page 78 of 438 table 5.5 number of states in interrupt handling routine execution status object of access external device * 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch si 1 4 6+2m 2 3+m branch address read sj stack manipulation sk legend m: number of wait states in an external device access. note: * cannot be used in this lsi. 5.7 usage notes 5.7.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5.6 shows an example in which the tgiea bit in the tpu's tier_0 register is cleared to 0. the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. rev. 0.5, 03/03, page 79 of 438 internal address bus internal write signal tciev tcfv tciv interrupt signal tier_0 write cycle by cpu tcivexception handling tier_0 address figure 5.6 contention between interrupt generation and disabling 5.7.2 instructions that disable interrupts the instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions are executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 when interrupts are disabled there are times when interrupt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction. rev. 0.5, 03/03, page 80 of 438 5.7.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 bsc0000a_000020020200 rev. 0.5, 03/03, page 81 of 438 section 6 bus controller the h8s/2600 cpu is driven by a system clock, denoted by the symbol . the bus controller controls a memory cycle and a bus cycle. different methods are used to access on-chip memory and on-chip peripheral modules. 6.1 basic timing the period from one rising edge of to the next is referred to as a "state." the memory cycle or bus cycle consists of one, two, three, or four states. different methods are used to access on-chip memory, on-chip support modules, and the external address space. 6.1.1 on-chip memory access timing (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 6.1 shows the on-chip memory access cycle. t1 internal address bus bus cycle address read data write data internal read signal internal data bus internal write signal internal data bus read access write access figure 6.1 on-chip memory access cycle rev. 0.5, 03/03, page 82 of 438 6.1.2 on-chip peripheral module access timing the on-chip peripheral modules, except for hcan are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. for details, refer to section 17, list of registers. figure 6.2 shows access timing for the on-chip peripheral modules. t1 t2 internal address bus bus cycle address read data write data internal read signal internal data bus internal write signal internal data bus read access write access figure 6.2 on-chip support module access cycle rev. 0.5, 03/03, page 83 of 438 6.1.3 on-chip hcan module access timing on-chip hcan module access is performed in four states. the data bus width is 16 bits. wait states can be inserted by means of a wait request from the hcan. on-chip hcan module access timing is shown in figure 6.3. t1 t3 t2 tw tw t4 internal address bus bus cycle address read data write data hcan read signal internal data bus hcan write signal internal data bus read write figure 6.3 on-chip hcan module access cycle (wait states inserted) rev. 0.5, 03/03, page 84 of 438 rev. 0.5, 03/03, page 85 of 438 section 7 i/o ports table 7.1 summarizes the port functions. the pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) used to read the pin states. the input-only ports do not have a dr or ddr register. ports a to d have a built-in input pull-up mos function and an input pull-up mos control register (pcr) to control the on/off state of the input pull-up mos. ports a to c include an open-drain control register (odr) that controls the on/off state of the output buffer pmos. all the i/o ports can drive a single ttl load and a 30 pf capacitive load. rev. 0.5, 03/03, page 86 of 438 table 7.1 port functions port description port and other functions name input/output and output type p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb p12/tiocc0/tclka p11/tiocb0 port 1 general i/o port also functioning as tpu i/o pins and interrupt input pins p10/tioca0 p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 port 4 general input port also functioning as a/d converter analog inputs p40/an0 p97/an15 p96/an14 p95/an13 p94/an12 p93/an11 p92/an10 p91/an9 port 9 general input port also functioning as a/d converter analog inputs p90/an8 pa3/sck2 pa2/rxd2 pa1/txd2 port a general i/o port also functioning as sci_2 i/o pins pa0 built-in input pull-up mos push-pull or open-drain output selectable rev. 0.5, 03/03, page 87 of 438 port description port and other functions name input/output and output type pb7/tiocb5 pb6/tioca5 pb5/tiocb4 pb4/tioca4 pb3/tiocd3 pb2/tiocc3 pb1/tiocb3 port b general i/o port also functioning as tpu_5, tpu_4, and tpu_3 i/o pins pb0/tioca3 built-in input pull-up mos push-pull or open-drain output selectable pc7 pc6 pc5/sck1/ irq5 pc4/rxd1 pc3/txd1 pc2/sck0/ irq4 pc1/rxd0 port c general i/o port also functioning as sci_1 and sci_0 i/o pins, and interrupt input pins pc0/txd0 built-in input pull-up mos push-pull or open-drain output selectable port d general i/o port pd7 built-in input pull-up mos pd6 pd5 pd4 pf7/ pf6 pf5 pf4 pf3/ adtrg / irq3 pf2 pf1 port f general i/o port also functioning as interrupt input pins, an a/d converter start trigger input pin, and a system clock output pin ( ) pf0/ irq2 rev. 0.5, 03/03, page 88 of 438 7.1 port 1 port 1 is an 8-bit i/o port that also has other functions. port 1 has the following registers. ? port 1 data direction register (p1ddr) ? port 1 data register (p1dr) ? port 1 register (port1) 7.1.1 port 1 data direction register (p1ddr) p1ddr specifies the input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 7.1.2 port 1 data register (p1dr) p1dr stores output data for port 1 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin is specified as a general purpose output port. rev. 0.5, 03/03, page 89 of 438 7.1.3 port 1 register (port1) port1 shows the pin states of the port 1. port1 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 p13 p12 p11 p10 undefined * undefined * undefined * undefined * undefined * undefined * undefined * undefined * r r r r r r r r if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins p17 to p10. 7.1.4 pin functions port 1 pins also function as tpu i/o pins and interrupt input pins. the correspondence between the register specification and the pin functions is shown below. table 7.2 p17 pin function tpu channel 2 setting * output input or initial value p17ddr ? 01 p17 input tiocb2 input pin function tiocb2 output tclkd input p17 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). rev. 0.5, 03/03, page 90 of 438 table 7.3 p16 pin function tpu channel 2 setting * output input or initial value p16ddr ? 01 p16 input tioca2 input pin function tioca2 output irq1 input p16 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.4 p15 pin function tpu channel 1 setting * output input or initial value p15ddr ? 01 p15 input tiocb1 input pin function tiocb1 output tclkc input p15 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.5 p14 pin function tpu channel 1 setting * output input or initial value p14ddr ? 01 p14 input tioca1 input pin function tioca1 output irq0 input p14 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). rev. 0.5, 03/03, page 91 of 438 table 7.6 p13 pin function tpu channel 0 setting * output input or initial value p13ddr ? 01 p13 input tiocd0 input pin function tiocd0 output tclkb input p13 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.7 p12 pin function tpu channel 0 setting * output input or initial value p12ddr ? 01 p12 input tiocc0 input pin function tiocc0 output tclka input p12 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.8 p11 pin function tpu channel 0 setting * output input or initial value p11ddr ? 01 p11 input pin function tiocb0 output tiocb0 input p11 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.9 p10 pin function tpu channel 0 setting * output input or initial value p10ddr ? 01 p10 input pin function tioca0 output tioca0 input p10 output note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). rev. 0.5, 03/03, page 92 of 438 7.2 port 4 port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins. port 4 has the following register. port 4 register (port4) 7.2.1 port 4 register (port4) port4 shows port 4 pin states. port4 cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p47 p46 p45 p44 p43 p42 p41 p40 undefined * undefined * undefined * undefined * undefined * undefined * undefined * undefined * r r r r r r r r the pin states are always read when a port 4 read is performed. note: * determined by the states of pins p47 to p40. 7.3 port 9 port 9 is an 8-bit input-only port. port 9 pins also function as a/d converter analog input pins. port 9 has the following register. port 9 register (port9) 7.3.1 port 9 register (port9) port9 shows port 9 pin states. port9 cannot be modified. rev. 0.5, 03/03, page 93 of 438 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 undefined * undefined * undefined * undefined * undefined * undefined * undefined * undefined * r r r r r r r r the pin states are always read when a port 9 read is performed. note: * determined by the states of pins p97 to p90. 7.4 port a port a is a 4-bit i/o port that also has other functions. port a has the following registers. ? port a data direction register (paddr) ? port a data register (padr) ? port a register (porta) ? port a pull-up mos control register (papcr) ? port a open-drain control register (paodr) 7.4.1 port a data direction register (paddr) paddr specifies whether the pins of port a are used for input or output. paddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved 3 2 1 0 pa3ddr pa2ddr pa1ddr pa0ddr 0 0 0 0 w w w w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port a pin an output pin. clearing this bit to 0 makes the pin an input pin. rev. 0.5, 03/03, page 94 of 438 7.4.2 port a data register (padr) padr stores output data for port a pins. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved the read value is undefined. 3 2 1 0 pa3dr pa2dr pa1dr pa0dr 0 0 0 0 r/w r/w r/w r/w output data for a pin is stored when the pin is specified as a general purpose output port. 7.4.3 port a register (porta) porta shows port a pin states. porta cannot be modified. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved the read value is undefined. 3 2 1 0 pa3 pa2 pa1 pa0 undefined * undefined * undefined * undefined * r r r r if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins pa3 to pa0. rev. 0.5, 03/03, page 95 of 438 7.4.4 port a pull-up mos control register (papcr) papcr controls the on/off state of the input pull-up mos of port a. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved the read value is undefined. 3 2 1 0 pa3pcr pa2pcr pa1pcr pa0pcr 0 0 0 0 r/w r/w r/w r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up mos for that pin. 7.4.5 port a open-drain control register (paodr) paodr specifies the output type of port a. bit bit name initial value r/w description 7 to 4 ? undefined ? reserved the read value is undefined. 3 2 1 0 pa3odr pa2odr pa1odr pa0odr 0 0 0 0 r/w r/w r/w r/w when a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output to open- drain and the pmos to the off state. clearing this bit to 0 specifies that to push-pull output. rev. 0.5, 03/03, page 96 of 438 7.4.6 pin functions port a pins also function as sci_2 i/o pins. the correspondence between the register specification and the pin functions is shown below. table 7.10 pa3 pin function cke1 0 1 c/a 0 1 ? cke0 0 1 ?? pa3ddr 0 1 ?? ? pin function pa3 input pa3 output sck2 output sck2 output sck2 input table 7.11 pa2 pin function re 0 1 pa2ddr 0 1 ? pin function pa2 input pa2 output rxd2 input table 7.12 pa1 pin function te 0 1 pa1ddr 0 1 ? pin function pa1 input pa1 output txd2 output table 7.13 pa0 pin function pa0ddr 0 1 pin function pa0 input pa0 output 7.5 port b port b is an 8-bit i/o port that also has other functions. port b has the following registers. ? port b data direction register (pbddr) ? port b data register (pbdr) ? port b register (portb) ? port b pull-up mos control register (pbpcr) ? port b open-drain control register (pbodr) rev. 0.5, 03/03, page 97 of 438 7.5.1 port b data direction register (pbddr) pbddr specifies whether the pins of port b are used for input or output. pbddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 7.5.2 port b data register (pbdr) pbdr stores output data for the port b pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin is specified as a general purpose output port. rev. 0.5, 03/03, page 98 of 438 7.5.3 port b register (portb) portb shows port b pin states. portb cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 undefined * undefined * undefined * undefined * undefined * undefined * undefined * undefined * r r r r r r r r if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins pb7 to pb0. 7.5.4 port b pull-up mos control register (pbpcr) pbpcr controls the on/off state of the input pull-up mos of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up mos for that pin. rev. 0.5, 03/03, page 99 of 438 7.5.5 port b open-drain control register (pbodr) pbodr specifies the output type of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w when a pin function is specified as an output port, setting the corresponding bit to 1 specifies pin output as open-drain and the pmos to the off state. clearing this bit to 0 specifies push-pull output. 7.5.6 pin functions port b pins also function as tpu i/o pins. the correspondence between the register specification and the pin functions is shown below. table 7.14 pb7 pin function tpu channel 5 setting * output input or initial value pb7ddr ? 01 pb7 input pb7 output pin function tiocb5 output tiocb5 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.15 pb6 pin function tpu channel 5 setting * output input or initial value pb6ddr ? 01 pb6 input pb6 output pin function tioca5 output tioca5 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). rev. 0.5, 03/03, page 100 of 438 table 7.16 pb5 pin function tpu channel 4 setting * output input or initial value pb5ddr ? 01 pb5 input pb5 output pin function tiocb4 output tiocb4 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.17 pb4 pin function tpu channel 4 setting * output input or initial value pb4ddr ? 01 pb4 input pb4 output pin function tioca4 output tioca4 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.18 pb3 pin function tpu channel 3 setting * output input or initial value pb3ddr ? 01 pb3 input pb3 output pin function tiocd3 output tiocd3 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.19 pb2 pin function tpu channel 3 setting * output input or initial value pb2ddr ? 01 pb2 input pb2 output pin function tiocc3 output tiocc3 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). rev. 0.5, 03/03, page 101 of 438 table 7.20 pb1 pin function tpu channel 3 setting * output input or initial value pb1ddr ? 01 pb1 input pb1 output pin function tiocb3 output tiocb3 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). table 7.21 pb0 pin function tpu channel 3 setting * output input or initial value pb0ddr ? 01 pb0 input pb0 output pin function tioca3 output tioca3 input note: * for details on the tpu channel specification, refer to section 8, 16-bit timer pulse unit (tpu). 7.6 port c port c is an 8-bit i/o port that also has other functions. port c has the following registers. ? port c data direction register (pcddr) ? port c data register (pcdr) ? port c register (portc) ? port c pull-up mos control register (pcpcr) ? port c open-drain control register (pcodr) 7.6.1 port c data direction register (pcddr) pcddr specifies whether the pins of port c are used for input or output. pcddr cannot be read; if it is, an undefined value will be read. rev. 0.5, 03/03, page 102 of 438 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr 0 0 0 0 0 0 0 0 w w w w w w w w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 7.6.2 port c data register (pcdr) pcdr stores output data for the port c pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin is specified as a general purpose output port. rev. 0.5, 03/03, page 103 of 438 7.6.3 port c register (portc) portc shows port c pin states. portc cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 undefined * undefined * undefined * undefined * undefined * undefined * undefined * undefined * r r r r r r r r if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins pc7 to pc0. 7.6.4 port c pull-up mos control register (pcpcr) pcpcr controls the on/off state of the input pull-up mos of port c. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w when a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up mos for that pin. rev. 0.5, 03/03, page 104 of 438 7.6.5 port c open-drain control register (pcodr) pcodr specifies an output type of port c. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pc7odr pc6odr pc5odr pc4odr pc3odr pc2odr pc1odr pc0odr 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w when a pin is specified as an output port, setting the corresponding bit to 1 specifies pin output as open- drain and the pmos to the off state. clearing this bit to 0 specifies push-pull output. 7.6.6 pin functions port c pins also function as sci_1 and sci_0 i/o and interrupt input. the correspondence between the register specification and the pin functions is shown below. table 7.22 pc7 pin function pc7ddr 0 1 pin function pc7 input pc7 output table 7.23 pc6 pin function pc6ddr 0 1 pin function pc6 input pc6 output table 7.24 pc5 pin function cke1 0 1 c/ a 01 ? cke0 0 1 ?? pc5ddr 0 1 ??? pc5 input pin function irq5 input pc5 output sck1 output sck1 output sck1 input rev. 0.5, 03/03, page 105 of 438 table 7.25 pc4 pin function re 0 1 pc4ddr 0 1 ? pin function pc4 input pc4 output rxd1 input table 7.26 pc3 pin function te 0 1 pc3ddr 0 1 ? pin function pc3 input pc3 output txd1 output table 7.27 pc2 pin function cke1 0 1 c/ a 01 ? cke0 0 1 ?? pc2ddr 0 1 ??? pc2 input pin function irq4 input pc2 output sck0 output sck0 output sck0 input table 7.28 pc1 pin function re 0 1 pc1ddr 0 1 ? pin function pc1 input pc1 output rxd0 input table 7.29 pc0 pin function te 0 1 pc0ddr 0 1 ? pin function pc0 input pc0 output txd0 output rev. 0.5, 03/03, page 106 of 438 7.7 port d port d is a 4-bit i/o port that also has other functions. port d has the following registers. ? port d data direction register (pdddr) ? port d data register (pddr) ? port d register (portd) ? port d pull-up mos control register (pdpcr) 7.7.1 port d data direction register (pdddr) pdddr specifies whether the pins of port d are used for input or output. pdddr cannot be read; if it is, an undefined value will be read. bit bit name initial value r/w description 7 6 5 4 pd7ddr pd6ddr pd5ddr pd4ddr 0 0 0 0 w w w w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port 1 pin an output pin. clearing this bit to 0 makes the pin an input pin. 3 to 0 ? undefined ? reserved the write value should always be 0. rev. 0.5, 03/03, page 107 of 438 7.7.2 port d data register (pddr) pddr stores output data for the port d pins. bit bit name initial value r/w description 7 6 5 4 pd7dr pd6dr pd5dr pd4dr 0 0 0 0 r/w r/w r/w r/w output data for a pin is stored when the pin is specified as a general purpose output port. 3 to 0 ? undefined ? reserved the read value is undefined. 7.7.3 port d register (portd) portd shows port d pin states. portd cannot be modified. bit bit name initial value r/w description 7 6 5 4 pd7 pd6 pd5 pd4 undefined * undefined * undefined * undefined * r r r r if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. 3 to 0 ? undefined ? reserved the read value is undefined. note: * determined by the states of pins pd7 to pd4. rev. 0.5, 03/03, page 108 of 438 7.7.4 port d pull-up mos control register (pdpcr) pdpcr controls on/off states of the input pull-up mos of port d. bit bit name initial value r/w description 7 6 5 4 pd7pcr pd6pcr pd5pcr pd4pcr 0 0 0 0 r/w r/w r/w r/w when the pin is in its input state, the input pull-up mos of the input pin is on when the corresponding bit is set to 1. 3 to 0 ? undefined ? reserved the write value should always be 0. 7.7.5 pin function port d is a 4-bit i/o port. table 7.30 pdn pin function pdnddr 0 1 pin function pdn input pdn output legend: n = 7 to 4 7.8 port f port f is an 8-bit i/o port that also has other functions. port f has the following registers. ? port f data direction register (pfddr) ? port f data register (pfdr) ? port f register (portf) 7.8.1 port f data direction register (pfddr) pfddr specifies whether the pins of port f are used for input or output. pfddr cannot be read; if it is, an undefined value will be read. rev. 0.5, 03/03, page 109 of 438 bit bit name initial value r/w description 7 pf7ddr 0 w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the pf7 pin a output pin. clearing this bit to 0 makes the pin an input pin. 6 5 4 3 2 1 0 pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr 0 0 0 0 0 0 0 w w w w w w w when a pin is specified as a general purpose i/o port, setting this bit to 1 makes the corresponding port f pin an output pin. clearing this bit to 0 makes the pin an input pin. 7.8.2 port f data register (pfdr) pfdr stores output data for the port f pins. bit bit name initial value r/w description 7? 0 r/wreserved the write value should always be 0. 6 5 4 3 2 1 0 pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w output data for a pin is stored when the pin is specified as a general purpose output port. rev. 0.5, 03/03, page 110 of 438 7.8.3 port f register (portf) portf shows port f pin states. portf cannot be modified. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 undefined * undefined * undefined * undefined * undefined * undefined * undefined * undefined * r r r r r r r r if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. note: * determined by the states of pins pf7 to pf0. 7.8.4 pin functions port f pins also function as external interrupt input ( irq2 and irq3 ), a/d trigger input ( adtrg ), and system clock output ( ). the correspondence between the register specification and the pin functions is shown below. table 7.31 pf7 pin function pf7ddr 0 1 pin function pf7 input output table 7.32 pf6 pin function pf6ddr 0 1 pin function pf6 input pf6 output table 7.33 pf5 pin function pf5ddr 0 1 pin function pf5 input pf5 output rev. 0.5, 03/03, page 111 of 438 table 7.34 pf4 pin function pf4ddr 0 1 pin function pf4 input pf4 output table 7.35 pf3 pin function pf3ddr 0 1 pf3 input adtrg input * 1 pin function irq3 input * 2 pf3 output notes: 1. adtrg input when trgs0 = trgs1 = 1. 2. when used as an external interrupt input pin, do not use as an i/o pin for another function. table 7.36 pf2 pin function pf2ddr 0 1 pin function pf2 input pf2 output table 7.37 pf1 pin function pf1ddr 0 1 pin function pf1 input pf1 output table 7.38 pf0 pin function pf0ddr 0 1 pf0 input pin function irq2 input pf0 output rev. 0.5, 03/03, page 112 of 438 timtpu0a_000020020200 rev. 0.5, 03/03, page 113 of 438 section 8 16-bit timer pulse unit (tpu) this lsi has an on-chip 16-bit timer pulse unit (tpu) comprised of six 16-bit timer channels. the function list of the 16-bit timer unit and its block diagram are shown in table 8.1 and figure 8.1, respectively. 8.1 features ? maximum 16-pulse input/output ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel: waveform output at compare match input capture function counter clear operation synchronous operation: multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture is possible register simultaneous input/output is possible by synchronous counter operation a maximum 15-phase pwm output is possible in combination with synchronous operation ? buffer operation settable for channels 0 and 3 ? phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? cascaded operation ? fast access via internal 16-bit bus ? 26 interrupt sources ? automatic transfer of register data ? a/d converter conversion start trigger can be generated ? module stop mode can be set rev. 0.5, 03/03, page 114 of 438 table 8.1 tpu functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock /1 /4 /16 /64 tclka tclkb tclkc tclkd /1 /4 /16 /64 /256 tclka tclkb /1 /4 /16 /64 /1024 tclka tclkb tclkc /1 /4 /16 /64 /256 /1024 /4096 tclka /1 /4 /16 /64 /1024 tclka tclkc /1 /4 /16 /64 /256 tclka tclkc tclkd general registers tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 tgra_3 tgrb_3 tgra_4 tgrb_4 tgra_5 tgrb_5 general registers/ buffer registers tgrc_0 tgrd_0 ??tgrc_3 tgrd_3 ?? i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output 1 output compare match output toggle output input capture function synchronous operation pwm mode phase counting mode ? ? buffer operation ?? ?? rev. 0.5, 03/03, page 115 of 438 item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 a/d converter trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture tgra_5 compare match or input capture interrupt sources 5 sources compare match or input capture 0a compare match or input capture 0b compare match or input capture 0c compare match or input capture 0d overflow 4 sources compare match or input capture 1a compare match or input capture 1b overflow underflow 4 sources compare match or input capture 2a compare match or input capture 2b overflow underflow 5 sources compare match or input capture 3a compare match or input capture 3b compare match or input capture 3c compare match or input capture 3d overflow 4 sources compare match or input capture 4a compare match or input capture 4b overflow underflow 4 sources compare match or input capture 5a compare match or input capture 5b overflow underflow legend : possible ? : not possible rev. 0.5, 03/03, page 116 of 438 channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb channel 5 tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 channel 2 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 control logic for channel 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control logic tstr tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 /1 /4 /16 /64 /256 /1024 /4096 tclka tclkb tclkc tclkd legend tstr: tsyr: tcr: tmdr: timer start register timer synchro register timer control register timer mode register timer i/o control registers (h, l) timer interrupt enable register timer status register timer general registers (a, b, c, d) tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d converter convertion start signal module data bus tgi3a tgi3b tgi3c tgi3d tciv3 tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u tmdr tsr tcr tiorh tier tiorl input/output pins channel 3: channel 4: channel 5: input/output pins channel 0: channel 1: channel 2: clock input internal clock: external clock: tior(h, l) tier: tsr: tgr(a, b, c, d): figure 8.1 block diagram of tpu rev. 0.5, 03/03, page 117 of 438 8.2 input/output pins table 8.2 pin configuration channel symbol i/o function all tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 tioca0 i/o tgra_0 input capture input/output compare output/pwm output pin tiocb0 i/o tgrb_0 input capture input/output compare output/pwm output pin tiocc0 i/o tgrc_0 input capture input/output compare output/pwm output pin tiocd0 i/o tgrd_0 input capture input/output compare output/pwm output pin 1 tioca1 i/o tgra_1 input capture input/output compare output/pwm output pin tiocb1 i/o tgrb_1 input capture input/output compare output/pwm output pin 2 tioca2 i/o tgra_2 input capture input/output compare output/pwm output pin tiocb2 i/o tgrb_2 input capture input/output compare output/pwm output pin 3 tioca3 i/o tgra_3 input capture input/output compare output/pwm output pin tiocb3 i/o tgrb_3 input capture input/output compare output/pwm output pin tiocc3 i/o tgrc_3 input capture input/output compare output/pwm output pin tiocd3 i/o tgrd_3 input capture input/output compare output/pwm output pin 4 tioca4 i/o tgra_4 input capture input/output compare output/pwm output pin tiocb4 i/o tgrb_4 input capture input/output compare output/pwm output pin 5 tioca5 i/o tgra_5 input capture input/output compare output/pwm output pin tiocb5 i/o tgrb_5 input capture input/output compare output/pwm output pin rev. 0.5, 03/03, page 118 of 438 8.3 register descriptions the tpu has the following registers for each channel. ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register h_0 (tiorh_0) ? timer i/o control register l_0 (tiorl_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) ? timer i/o control register h_3 (tiorh_3) ? timer i/o control register l_3 (tiorl_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) rev. 0.5, 03/03, page 119 of 438 ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? timer control register_4 (tcr_4) ? timer mode register_4 (tmdr_4) ? timer i/o control register _4 (tior_4) ? timer interrupt enable register_4 (tier_4) ? timer status register_4 (tsr_4) ? timer counter_4 (tcnt_4) ? timer general register a_4 (tgra_4) ? timer general register b_4 (tgrb_4) ? timer control register_5 (tcr_5) ? timer mode register_5 (tmdr_5) ? timer i/o control register_5 (tior_5) ? timer interrupt enable register_5 (tier_5) ? timer status register_5 (tsr_5) ? timer counter_5 (tcnt_5) ? timer general register a_5 (tgra_5) ? timer general register b_5 (tgrb_5) common registers ? timer start register (tstr) ? timer synchro register (tsyr) rev. 0.5, 03/03, page 120 of 438 8.3.1 timer control register (tcr) tcr controls the tcnt operation for each channel. the tpu has a total of six tcr registers, one for each channel (channel 0 to 5). tcr register settings should be conducted only when tcnt operation is stopped. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 0 to 2 these bits select the tcnt counter clearing source. see tables 8.3 and 8.4 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 0 and 1 these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: count at rising edge 01: count at falling edge 1x: count at both edges legend x: don?t care 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 0 to 2 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables 8.5 to 8.10 for details. rev. 0.5, 03/03, page 121 of 438 table 8.3 cclr0 to cclr2 (channels 0 and 3) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0, 3 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is set by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. table 8.4 cclr0 to cclr2 (channels 1, 2, 4, and 5) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is selected by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified. rev. 0.5, 03/03, page 122 of 438 table 8.5 tpsc0 to tpsc2 (channel 0) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input table 8.6 tpsc0 to tpsc2 (channel 1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on /256 1 counts on tcnt2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. rev. 0.5, 03/03, page 123 of 438 table 8.7 tpsc0 to tpsc2 (channels 2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on /1024 note: this setting is ignored when channel 2 is in phase counting mode. table 8.8 tpsc0 to tpsc2 (channel 3) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on /1024 1 0 internal clock: counts on /256 1 internal clock: counts on /4096 rev. 0.5, 03/03, page 124 of 438 table 8.9 tpsc0 to tpsc2 (channel 4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 4 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /1024 1 counts on tcnt5 overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. table 8.10 tpsc0 to tpsc2 (channel 5) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 5 0 0 0 internal clock: counts on /1 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /256 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode. rev. 0.5, 03/03, page 125 of 438 8.3.2 timer mode register (tmdr) tmdr sets the operating mode of each channel. the tpu has six tmdr registers, one for each channel. tmdr register settings should be changed only when tcnt operation is stopped. bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1 and cannot be modified. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation 4 bfa 0 r/w buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. 0: tgra operates normally 1: tgra and tgrc used together for buffer operation 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 0 to 3 these bits are used to set the timer operating mode. md3 is a reserved bit. in a write, it should always be written with 0. see table 8.11 for details. rev. 0.5, 03/03, page 126 of 438 table 8.11 md0 to md3 bit 3 md3 * 1 bit 2 md2 * 2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 xxx? legend x: don?t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. rev. 0.5, 03/03, page 127 of 438 8.3.3 timer i/o control register (tior) tior controls tgr. the tpu has eight tior registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. care is required as tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. tiorh_0, tior_1, tior_2, tiorh_3, tior_4, tior_5 bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 0 0 0 0 r/w r/w r/w r/w i/o control b0 to b3 specify the function of tgrb. 3 2 1 0 ioa3 ioa2 ioa1 ioa0 0 0 0 0 r/w r/w r/w r/w i/o control a0 to a3 specify the function of tgra. tiorl_0, tiorl_3 bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 0 0 0 0 r/w r/w r/w r/w i/o control d0 to d3 specify the function of tgrd. 3 2 1 0 ioc3 ioc2 ioc1 ioc0 0 0 0 0 r/w r/w r/w r/w i/o control c0 to c3 specify the function of tgrc. rev. 0.5, 03/03, page 128 of 438 table 8.12 tiorh_0 (channel 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tiocb0 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocb0 pin input capture at rising edge 1 capture input source is tiocb0 pin input capture at falling edge 1 x capture input source is tiocb0 pin input capture at both edges 1xx input capture register capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down * legend x: don?t care note: * when bits tpsc0 to tpsc2 in tcr_1 are set to b'000 and /1 is used as the tcnt_1 count clock, this setting is invalid and input capture is not generated. rev. 0.5, 03/03, page 129 of 438 table 8.13 tiorl_0 (channel 0) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tiocd0 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register * 2 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocd0 pin input capture at rising edge 1 capture input source is tiocd0 pin input capture at falling edge 1 x capture input source is tiocd0 pin input capture at both edges 1xx input capture register * 2 capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down * 1 legend x: don?t care notes: 1. when bits tpsc0 to tpsc2 in tcr_1 are set to b'000 and /1 is used as the tcnt_1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 0.5, 03/03, page 130 of 438 table 8.14 tior_1 (channel 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tiocb1 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocb1 pin input capture at rising edge 1 capture input source is tiocb1 pin input capture at falling edge 1 x capture input source is tiocb1 pin input capture at both edges 1xx input capture register tgrc_0 compare match/ input capture input capture at generation of tgrc_0 compare match/input capture legend x: don?t care rev. 0.5, 03/03, page 131 of 438 table 8.15 tior_2 (channel 2) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tiocb2 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 x 0 0 capture input source is tiocb2 pin input capture at rising edge 1 capture input source is tiocb2 pin input capture at falling edge 1x input capture register capture input source is tiocb2 pin input capture at both edges legend x: don?t care rev. 0.5, 03/03, page 132 of 438 table 8.16 tiorh_3 (channel 3) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_3 function tiocb3 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocb3 pin input capture at rising edge 1 capture input source is tiocb3 pin input capture at falling edge 1 x capture input source is tiocb3 pin input capture at both edges 1xx input capture register capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down * legend x: don?t care note: * when bits tpsc0 to tpsc2 in tcr_4 are set to b'000 and /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. rev. 0.5, 03/03, page 133 of 438 table 8.17 tiorl_3 (channel 3) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_3 function tiocd3 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register * 2 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocd3 pin input capture at rising edge 1 capture input source is tiocd3 pin input capture at falling edge 1 x capture input source is tiocd3 pin input capture at both edges 1xx input capture register * 2 capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down * 1 legend x: don?t care notes: 1. when bits tpsc0 to tpsc2 in tcr_4 are set to b'000 and /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr_3 is set to 1 and tgrd_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 0.5, 03/03, page 134 of 438 table 8.18 tior_4 (channel 4) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_4 function tiocb4 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocb4 pin input capture at rising edge 1 capture input source is tiocb4 pin input capture at falling edge 1 x capture input source is tiocb4 pin input capture at both edges 1xx input capture register capture input source is tgrc_3 compare match/input capture input capture at generation of tgrc_3 compare match/input capture legend x: don?t care rev. 0.5, 03/03, page 135 of 438 table 8.19 tior_5 (channel 5) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_5 function tiocb5 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 x 0 0 capture input source is tiocb5 pin input capture at rising edge 1 capture input source is tiocb5 pin input capture at falling edge 1x input capture register capture input source is tiocb5 pin input capture at both edges legend x: don?t care rev. 0.5, 03/03, page 136 of 438 table 8.20 tiorh_0 (channel 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioca0 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca0 pin input capture at rising edge 1 capture input source is tioca0 pin input capture at falling edge 1 x capture input source is tioca0 pin input capture at both edges 1xx input capture register capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down * legend x: don?t care note: * when bits tpsc0 to tpsc2 in tcr_1 are set to b'000 and /1 is used as the tcnt_1 count clock, this setting is invalid and input capture is not generated. rev. 0.5, 03/03, page 137 of 438 table 8.21 tiorl_0 (channel 0) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tiocc0 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register * initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocc0 pin input capture at rising edge 1 capture input source is tiocc0 pin input capture at falling edge 1 x capture input source is tiocc0 pin input capture at both edges 1xx input capture register * capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down legend x: don?t care note: * when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 0.5, 03/03, page 138 of 438 table 8.22 tior_1 (channel 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioca1 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca1 pin input capture at rising edge 1 capture input source is tioca1 pin input capture at falling edge 1 x capture input source is tioca1 pin input capture at both edges 1xx input capture register capture input source is tgra_0 compare match/input capture input capture at generation of channel 0/tgra_0 compare match/input capture legend x: don?t care rev. 0.5, 03/03, page 139 of 438 table 8.23 tior_2 (channel 2) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioca2 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 x 0 0 capture input source is tioca2 pin input capture at rising edge 1 capture input source is tioca2 pin input capture at falling edge 1x input capture register capture input source is tioca2 pin input capture at both edges legend x: don?t care rev. 0.5, 03/03, page 140 of 438 table 8.24 tiorh_3 (channel 3) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_3 function tioca3 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca3 pin input capture at rising edge 1 capture input source is tioca3 pin input capture at falling edge 1 x capture input source is tioca3 pin input capture at both edges 1xx input capture register capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down * legend x: don?t care note: * when bits tpsc0 to tpsc2 in tcr_4 are set to b'000 and /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. rev. 0.5, 03/03, page 141 of 438 table 8.25 tiorl_3 (channel 3) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_3 function tiocc3 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register * 2 initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tiocc3 pin input capture at rising edge 1 capture input source is tiocc3 pin input capture at falling edge 1 x capture input source is tiocc3 pin input capture at both edges 1xx input capture register * 2 capture input source is channel 4/count clock input capture at tcnt_4 count-up/count-down * 1 legend x: don?t care notes: 1. when bits tpsc0 to tpsc2 in tcr_4 are set to b'000 and /1 is used as the tcnt_4 count clock, this setting is invalid and input capture is not generated. 2. when the bfa bit in tmdr_3 is set to 1 and tgrc_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 0.5, 03/03, page 142 of 438 table 8.26 tior_4 (channel 4) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_4 function tioca4 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 0 0 0 capture input source is tioca4 pin input capture at rising edge 1 capture input source is tioca4 pin input capture at falling edge 1 x capture input source is tioca4 pin input capture at both edges 1xx input capture register capture input source is tgra_3 compare match/input capture input capture at generation of tgra_3 compare match/input capture legend x: don?t care rev. 0.5, 03/03, page 143 of 438 table 8.27 tior_5 (channel 5) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_5 function tioca5 pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 output compare register initial output is 1 toggle output at compare match 1 x 0 0 capture input source is tioca5 pin input capture at rising edge 1 capture input source is tioca5 pin input capture at falling edge 1x input capture register capture input source is tioca5 pin input capture at both edges legend x: don?t care rev. 0.5, 03/03, page 144 of 438 8.3.4 timer interrupt enable register (tier) tier controls enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. bit bit name initial value r/w description 7 ttge 0 r/w a/d conversion start request enable enables or disables generation of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 5 tcieu 0 r/w underflow interrupt enable enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled 4 tciev 0 r/w overflow interrupt enable enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled 3 tgied 0 r/w tgr interrupt enable d enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgid) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled rev. 0.5, 03/03, page 145 of 438 bit bit name initial value r/w description 2 tgiec 0 r/w tgr interrupt enable c enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests (tgic) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled 8.3.5 timer status register (tsr) tsr indicates the status of each channel. the tpu has six tsr registers, one for each channel. bit bit name initial value r/w description 7 tcfd 1 r count direction flag status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. 0: tcnt counts down 1: tcnt counts up 6 ? 1 ? reserved this bit is always read as 1 and cannot be modified. rev. 0.5, 03/03, page 146 of 438 bit bit name initial value r/w description 5 tcfu 0 r/(w) * underflow flag status flag that indicates that tcnt underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 4 tcfv 0 r/(w) * overflow flag status flag that indicates that tcnt overflow has occurred. [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfv after reading tcfv = 1 3tgfd 0 r/(w) * input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. [setting conditions] when tcnt = tgrd and tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal and tgrd is functioning as input capture register [clearing condition] when 0 is written to tgfd after reading tgfd = 1 rev. 0.5, 03/03, page 147 of 438 bit bit name initial value r/w description 2tgfc 0 r/(w) * input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. [setting conditions] when tcnt = tgrc and tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal and tgrc is functioning as input capture register [clearing condition] when 0 is written to tgfc after reading tgfc = 1 1tgfb 0 r/(w) * input capture/output compare flag b status flag that indicates the occurrence of tgrb input capture or compare match. [setting conditions] when tcnt = tgrb and tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal and tgrb is functioning as input capture register [clearing condition] when 0 is written to tgfb after reading tgfb = 1 0tgfa 0 r/(w) * input capture/output compare flag a status flag that indicates the occurrence of tgra input capture or compare match. [setting conditions] when tcnt = tgra and tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal and tgra is functioning as input capture register [clearing condition] when 0 is written to tgfa after reading tgfa = 1 note: * only 0 can be written for clearing the flag. rev. 0.5, 03/03, page 148 of 438 8.3.6 timer counter (tcnt) the tcnt registers are 16-bit readable/writable counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 8.3.7 timer general register (tgr) the tgr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. the tpu has 16 tgr registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. tgr buffer register combinations are tgra? tgrc and tgrb?tgrd. 8.3.8 timer start register (tstr) tstr selects the tcnt operation/stoppage for channels 0 to 5. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved only 0 should be written to these bits. 5 4 3 2 1 0 cst5 cst4 cst3 cst2 cst1 cst0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w counter start 0 to 5 (cst0 to cst5) these bits select operation or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_0 to tcnt_5 count operation is stopped 1: tcnt_0 to tcnt_5 performs count operation rev. 0.5, 03/03, page 149 of 438 8.3.9 timer synchro register (tsyr) tsyr selects independent operation or synchronous operation for channels 0 to 5 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. bit bit name initial value r/w description 7 6 ? ? 0 0 r/w r/w reserved only 0 should be written to these bits. 5 4 3 2 1 0 sync5 sync4 sync3 sync2 sync1 sync0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w timer synchro 0 to 5 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_0 to tcnt_5 operates independently (tcnt presetting /clearing is unrelated to other channels) 1: tcnt_0 to tcnt_5 performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible rev. 0.5, 03/03, page 150 of 438 8.4 operation 8.4.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. 1. example of count operation setting procedure figure 8.2 shows an example of the count operation setting procedure. operation selection select counter clock periodic counter select counter clearing source select output compare register set period free-running counter start count operation rev. 0.5, 03/03, page 151 of 438 2. free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 8.3 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 8.3 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr0 to cclr2 in tcr. after the settings have been made, tcnt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. figure 8.4 illustrates periodic counter operation. rev. 0.5, 03/03, page 152 of 438 tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software initiation figure 8.4 periodic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. example of setting procedure for waveform output by compare match figure 8.5 shows an example of the setting procedure for waveform output by compare match output selection select waveform output mode set output timing start count operation rev. 0.5, 03/03, page 153 of 438 2. examples of waveform output operation figure 8.6 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made such that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 8.6 example of 0 output/1 output operation figure 8.7 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 8.7 example of toggle output operation rev. 0.5, 03/03, page 154 of 438 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. note: when another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if /1 is selected. 1. example of input capture operation setting procedure figure 8.8 shows an example of the input capture operation setting procedure. input selection select input capture input start count designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. set the cst bit in tstr to 1 to start the count operation. [1] [2] [1] [2] figure 8.8 example of input capture operation setting procedure rev. 0.5, 03/03, page 155 of 438 2. example of input capture operation figure 8.9 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, the falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb time figure 8.9 example of input capture operation rev. 0.5, 03/03, page 156 of 438 8.4.2 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 8.10 shows an example of the synchronous operation setting procedure. no yes synchronous operation selection set synchronous operation synchronous presetting set tcnt rev. 0.5, 03/03, page 157 of 438 example of synchronous operation: figure 8.11 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgrb_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting and synchronous clearing by tgrb_0 compare match are performed for channel 0 to 2 tcnt counters, and the data set in tgrb_0 is used as the pwm cycle. for details of pwm modes, see section 8.4.5, pwm modes. tcnt0 to tcnt2 values h'0000 tioca0 tioca1 tgrb_0 synchronous clearing by tgrb_0 compare match tgra_2 tgra_1 tgrb_2 tgra_0 tgrb_1 tioca2 time figure 8.11 example of synchronous operation 8.4.3 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 8.28 shows the register combinations used in buffer operation. rev. 0.5, 03/03, page 158 of 438 table 8.28 register combinations in buffer operation channel timer general register buffer register 0 tgra_0 tgrc_0 tgrb_0 tgrd_0 3 tgra_3 tgrc_3 tgrb_3 tgrd_3 ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 8.12. buffer register timer general register tcnt comparator compare match signal figure 8.12 compare match buffer operation ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 8.13. buffer register timer general register tcnt input capture signal figure 8.13 input capture buffer operation rev. 0.5, 03/03, page 159 of 438 example of buffer operation setting procedure: figure 8.14 shows an example of the buffer operation setting procedure. buffer operation select tgr function set buffer operation start count rev. 0.5, 03/03, page 160 of 438 tcnt value tgrb_0 h'0000 tgrc_0 tgra_0 h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgra_0 h'0450 h'0200 transfer time figure 8.15 example of buffer operation (1) 2. when tgr is an input capture register figure 8.16 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon the occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 8.16 example of buffer operation (2) rev. 0.5, 03/03, page 161 of 438 8.4.4 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt_2 (tcnt_5) as set in bits tpsc0 to tpsc2 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 8.29 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. table 8.29 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt_1 tcnt_2 channels 4 and 5 tcnt_4 tcnt_5 example of cascaded operation setting procedure: figure 8.17 shows an example of the setting procedure for cascaded operation. cascaded operation set cascading start count rev. 0.5, 03/03, page 162 of 438 tcnt_2 clock tcnt_2 h'ffff h'0000 h'0001 tioca1, tioca2 tgra_1 h'03a2 tgra_2 h'0000 tcnt_1 clock tcnt_1 h'03a1 h'03a2 figure 8.18 example of cascaded operation (1) figure 8.19 illustrates the operation when tcnt_2 overflow/underflow counting has been set for tcnt_1 and phase counting mode has been designated for channel 2. tcnt_1 is incremented by tcnt_2 overflow and decremented by tcnt_2 underflow. tclka tcnt_2 fffd tcnt_1 0001 tclkb fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 8.19 example of cascaded operation (2) 8.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. the output level can be selected as 0, 1, or toggle output in response to a compare match of each tgr. tgr registers settings can be used to output a pwm waveform in the range of 0% to 100% duty. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. rev. 0.5, 03/03, page 163 of 438 ? pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa0 to ioa3 and ioc0 to ioc3 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob0 to iob3 and iod0 to iod3 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible in combination use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 8.30. table 8.30 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgra_0 tioca0 tioca0 tgrb_0 tiocb0 tgrc_0 tiocc0 tiocc0 tgrd_0 tiocd0 1 tgra_1 tioca1 tioca1 tgrb_1 tiocb1 2 tgra_2 tioca2 tioca2 tgrb_2 tiocb2 3 tgra_3 tioca3 tioca3 tgrb_3 tiocb3 tgrc_3 tiocc3 tiocc3 tgrd_3 tiocd3 4 tgr4a_4 tioca4 tioca4 tgr4b_4 tiocb4 5 tgra_5 tioca5 tioca5 tgrb_5 tiocb5 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set. rev. 0.5, 03/03, page 164 of 438 example of pwm mode setting procedure: figure 8.20 shows an example of the pwm mode setting procedure. pwm mode select counter clock select counter clearing source select waveform output level set tgr set pwm mode start count rev. 0.5, 03/03, page 165 of 438 figure 8.22 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgrb_1 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_0 to tgrd_0, tgra_1), outputting a 5-phase pwm waveform. in this case, the value set in tgrb_1 is used as the cycle, and the values set in the other tgrs are used as the duty levels. tcnt value tgrb_1 h'0000 tioca0 counter cleared by tgrb_1 compare match time tgra_1 tgrd_0 tgrc_0 tgrb_0 tgra_0 tiocb0 tiocc0 tiocd0 tioca1 figure 8.22 example of pwm mode operation (2) rev. 0.5, 03/03, page 166 of 438 figure 8.23 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 8.23 example of pwm mode operation (3) rev. 0.5, 03/03, page 167 of 438 8.4.6 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc0 to tpsc2 and bits ckeg0 and ckeg1 in tcr. however, the functions of bits cclr0 and cclr1 in tcr, and of tior, tier, and tgr, are valid, and input capture/compare match and interrupt functions can be used. this can be used for two-phase encoder pulse input. if overflow occurs when tcnt is counting up, the tcfv flag in tsr is set; if underflow occurs when tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag reveals whether tcnt is counting up or down. table 8.31 shows the correspondence between external clock pins and channels. table 8.31 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 8.24 shows an example of the phase counting mode setting procedure. phase counting mode select phase counting mode start count rev. 0.5, 03/03, page 168 of 438 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. 1. phase counting mode 1 figure 8.25 shows an example of phase counting mode 1 operation, and table 8.32 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka(channels 1 and 5) tclkc(channels 2 and 4) tclkb(channels 1 and 5) tclkd(channels 2 and 4) figure 8.25 example of phase counting mode 1 operation table 8.32 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level legend : rising edge : falling edge rev. 0.5, 03/03, page 169 of 438 2. phase counting mode 2 figure 8.26 shows an example of phase counting mode 2 operation, and table 8.33 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka(channels 1 and 5) tclkc(channels 2 and 4) tclkb(channels 1 and 5) tclkd(channels 2 and 4) figure 8.26 example of phase counting mode 2 operation table 8.33 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don?t care low level don?t care low level don?t care high level up-count high level don?t care low level don?t care high level don?t care low level down-count legend : rising edge : falling edge rev. 0.5, 03/03, page 170 of 438 3. phase counting mode 3 figure 8.27 shows an example of phase counting mode 3 operation, and table 8.34 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka(channels 1 and 5) tclkc(channels 2 and 4) tclkb(channels 1 and 5) tclkd(channels 2 and 4) figure 8.27 example of phase counting mode 3 operation table 8.34 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don?t care low level don?t care low level don?t care high level up-count high level down-count low level don?t care high level don?t care low level don?t care legend : rising edge : falling edge rev. 0.5, 03/03, page 171 of 438 4. phase counting mode 4 figure 8.28 shows an example of phase counting mode 4 operation, and table 8.35 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka(channels 1 and 5) tclkc(channels 2 and 4) tclkb(channels 1 and 5) tclkd(channels 2 and 4) figure 8.28 example of phase counting mode 4 operation table 8.35 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level don?t care high level high level down-count low level high level don?t care low level legend : rising edge : falling edge rev. 0.5, 03/03, page 172 of 438 phase counting mode application example: figure 8.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgrc_0 compare match; tgra_0 and tgrc_0 are used for the compare match function and are set with the speed control period and position control period. tgrb_0 is used for input capture, with tgrb_0 and tgrd_0 operating in buffer mode. the channel 1 counter input clock is designated as the tgrb_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. tgra_1 and tgrb_1 for channel 1 are designated for input capture, and channel 0 tgra_0 and tgrc_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. this procedure enables the accurate detection of position and speed. rev. 0.5, 03/03, page 173 of 438 tcnt_1 tcnt_0 channel 1 tgra_1 (speed period capture) tgra_0 (speed control period) tgrb_1 (speed period capture) tgrc_0 (position control period) tgrb_0 (pulse width capture) tgrd_0 (buffer operation) channel 0 tclka tclkb edge detection circuit + - + - figure 8.29 phase counting mode application example 8.5 interrupts there are three kinds of tpu interrupt source; tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. for details, see section 5, interrupt controller. table 8.36 lists the tpu interrupt sources. rev. 0.5, 03/03, page 174 of 438 table 8.36 tpu interrupts channel name interrupt source interrupt flag 0 tgi0a tgra_0 input capture/compare match tgfa_0 tgi0b tgrb_0 input capture/compare match tgfb_0 tgi0c tgrc_0 input capture/compare match tgfc_0 tgi0d tgrd_0 input capture/compare match tgfd_0 tci0v tcnt_0 overflow tcfv_0 1 tgi1a tgra_1 input capture/compare match tgfa_1 tgi1b tgrb_1 input capture/compare match tgfb_1 tci1v tcnt_1 overflow tcfv_1 tci1u tcnt_1 underflow tcfu_1 2 tgi2a tgra_2 input capture/compare match tgfa_2 tgi2b tgrb_2 input capture/compare match tgfb_2 tci2v tcnt_2 overflow tcfv_2 tci2u tcnt_2 underflow tcfu_2 3 tgi3a tgra_3 input capture/compare match tgfa_3 tgi3b tgrb_3 input capture/compare match tgfb_3 tgi3c tgrc_3 input capture/compare match tgfc_3 tgi3d tgrd_3 input capture/compare match tgfd_3 tci3v tcnt_3 overflow tcfv_3 4 tgi4a tgra_4 input capture/compare match tgfa_4 tgi4b tgrb_4 input capture/compare match tgfb_4 tci4v tcnt_4 overflow tcfv_4 tci4u tcnt_4 underflow tcfu_4 5 tgi5a tgra_5 input capture/compare match tgfa_5 tgi5b tgrb_5 input capture/compare match tgfb_5 tci5v tcnt_5 overflow tcfv_5 tci5u tcnt_5 underflow tcfu_5 note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. rev. 0.5, 03/03, page 175 of 438 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four underflow interrupts, one each for channels 1, 2, 4, and 5. 8.6 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to begin a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is begun. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel. rev. 0.5, 03/03, page 176 of 438 8.7 operation timing 8.7.1 input/output timing tcnt count timing: figure 8.30 shows tcnt count timing in internal clock operation, and figure 8.31 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n-1 n n+1 n+2 falling edge rising edge figure 8.30 count timing in internal clock operation tcnt tcnt input clock external clock n-1 n n+1 n+2 falling edge rising edge falling edge figure 8.31 count timing in external clock operation output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin. after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 8.32 shows output compare output timing. rev. 0.5, 03/03, page 177 of 438 tgr tcnt tcnt input clock n n n+1 compare match signal tioc pin figure 8.32 output compare output timing input capture signal timing: figure 8.33 shows input capture signal timing. tcnt input capture input n n+1 n+2 n n+2 tgr input capture signal figure 8.33 input capture input signal timing rev. 0.5, 03/03, page 178 of 438 timing for counter clearing by compare match/input capture: figure 8.34 shows the timing when counter clearing on compare match is specified, and figure 8.35 shows the timing when counter clearing on input capture is specified. tcnt counter clear signal compare match signal tgr n n h'0000 figure 8.34 counter clear timing (compare match) tcnt counter clear signal input capture signal tgr n h'0000 n figure 8.35 counter clear timing (input capture) rev. 0.5, 03/03, page 179 of 438 buffer operation timing: figures 8.36 and 8.37 show the timing in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd nn n n n+1 figure 8.36 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal tgrc, tgrd n n n n+1 n n n+1 figure 8.37 buffer operation timing (input capture) rev. 0.5, 03/03, page 180 of 438 8.7.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 8.38 shows the timing for setting of the tgf flag in tsr on compare match, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n+1 compare match signal tgf flag tgi interrupt figure 8.38 tgi interrupt timing (compare match) tgf flag setting timing in case of input capture: figure 8.39 shows the timing for setting of the tgf flag in tsr on input capture, and tgi interrupt request signal timing. tgr tcnt input capture signal n n tgf flag tgi interrupt figure 8.39 tgi interrupt timing (input capture) rev. 0.5, 03/03, page 181 of 438 tcfv flag/tcfu flag setting timing: figure 8.40 shows the timing for setting of the tcfv flag in tsr on overflow, and tciv interrupt request signal timing. figure 8.41 shows the timing for setting of the tcfu flag in tsr on underflow, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt figure 8.40 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt figure 8.41 tciu interrupt setting timing rev. 0.5, 03/03, page 182 of 438 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. figure 8.42 shows the timing for status flag clearing by the cpu. status flag write signal address tsr address interrupt request signal tsr write cycle t1 t2 figure 8.42 timing for status flag clearing by cpu rev. 0.5, 03/03, page 183 of 438 8.8 usage notes 8.8.1 module stop mode setting tpu operation can be disabled or enabled using the module stop control register. the initial setting is for tpu operation to be halted. register access is enabled by clearing module stop mode. for details, refer to section 16, power-down modes. 8.8.2 input clock restrictions the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly at narrower pulse widths. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 8.43 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 8.43 phase difference, overlap, and pulse width in phase counting mode rev. 0.5, 03/03, page 184 of 438 8.8.3 caution on period setting when counter clearing on compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = (n + 1) where f : counter frequency : operating frequency n : tgr set value 8.8.4 contention between tcnt write and clear operations if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 8.44 shows the timing in this case. counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 8.44 contention between tcnt write and clear operations rev. 0.5, 03/03, page 185 of 438 8.8.5 contention between tcnt write and increment operations if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 8.45 shows the timing in this case. tcnt input clock write signal address tcnt address tcnt tcnt write cycle t1 t2 n m tcnt write data figure 8.45 contention between tcnt write and increment operations 8.8.6 contention between tgr write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the previous value is written. figure 8.46 shows the timing in this case. rev. 0.5, 03/03, page 186 of 438 compare match signal write signal address tgr address tcnt tgr write cycle t1 t2 n m tgr write data tgr n n+1 inhibited figure 8.46 contention between tgr write and compare match 8.8.7 contention between buffer register write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the data that is transferred to tgr by the buffer operation will be that in the buffer prior to the write. figure 8.47 shows the timing in this case. compare match signal write signal address buffer register address buffer register tgr write cycle t1 t2 n tgr n m buffer register write data figure 8.47 contention between buffer register write and compare match rev. 0.5, 03/03, page 187 of 438 8.8.8 contention between tgr read and input capture if an input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be that in the buffer after input capture transfer. figure 8.48 shows the timing in this case. input capture signal read signal address tgr address tgr tgr read cycle t1 t2 m internal data bus x m figure 8.48 contention between tgr read and input capture 8.8.9 contention between tgr write and input capture if an input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 8.49 shows the timing in this case. rev. 0.5, 03/03, page 188 of 438 input capture signal write signal address tcnt tgr write cycle t1 t2 m tgr m tgr address figure 8.49 contention between tgr write and input capture 8.8.10 contention between buffer register write and input capture if an input capture signal is generated in the t2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 8.50 shows the timing in this case. input capture signal write signal address tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 8.50 contention between buffer register write and input capture rev. 0.5, 03/03, page 189 of 438 8.8.11 contention between overflow/underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 8.51 shows the operation timing when a tgr compare match is specified as the clearing source, and when h'ffff is set in tgr. counter clear signal tcnt input clock tcnt tgf disabled tcfv h'ffff h'0000 figure 8.51 contention between overflow and counter clearing rev. 0.5, 03/03, page 190 of 438 8.8.12 contention between tcnt write and overflow/underflow if there is an up-count or down-count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 8.52 shows the operation timing when there is contention between tcnt write and overflow. write signal address tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag figure 8.52 contention between tcnt write and overflow 8.8.13 multiplexing of i/o pins in this lsi, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. 8.8.14 interrupts in module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source. interrupts should therefore be disabled before entering module stop mode. wdt0100a_000020020200 rev. 0.5, 03/03, page 191 of 438 section 9 watchdog timer (wdt) this lsi has a two-channel watchdog timer (wdt_0, wdt_1). wdt is an 8-bit timer that can generate an internal reset signal for this lsi if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. the block diagrams of the wdt_0 and wdt_1 are shown in figures 9.1 and 9.2, respectively. 9.1 features ? selectable from eight counter input clocks (wdt_0) or sixteen counter input clocks (wdt_1) ? switchable between watchdog timer mode and interval timer mode in watchdog timer mode ? if the counter overflows, it is possible to select whether this lsi is internally reset or not or whether an internal nmi interrupt is generated or not. in interval timer mode ? if the counter overflows, the wdt generates an interval timer interrupt (wovi). rev. 0.5, 03/03, page 192 of 438 overflow interrupt control wovi (interrupt request signal) internal reset signal * reset control rstcsr tcnt_0 tcsr_0 /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock select internal clock sources bus interface module bus tcsr_0 tcnt_0 rstcsr note: * an internal reset signal can be generated by setting the register. : timer control/status register_0 : timer counter_0 : reset control/status register wdt legend internal bus figure 9.1 block diagram of wdt_0 overflow interrupt control wovi (interrupt request signal) internal nmi interrupt request signal internal reset signal * reset control tcnt_1 tcsr_1 /2 /64 /128 /512 /2048 /8192 /32768 /131072 sub/2 sub/4 sub/8 sub/16 sub/32 sub/64 sub/128 sub/256 clock clock select internal clock bus interface module bus tcsr_1 tcnt_1 note: * an internal reset signal can be generated by setting the register. : timer control/status register_1 : timer counter_1 wdt legend internal bus figure 9.2 block diagram of wdt_1 rev. 0.5, 03/03, page 193 of 438 9.2 register descriptions the wdt has the following registers. to prevent accidental overwriting, tcsr, tcnt, and rstcsr have to be written to by a different method to normal registers. for details, refer to section 9.5.1, notes on register access. ? timer counter_0 (tcnt_0) ? timer control/status register_0 (tcsr_0) ? timer counter_1 (tcnt_1) ? timer control/status register_1 (tcsr_1) ? reset control/status register (rstcsr) 9.2.1 timer counter (tcnt) tcnt is an 8-bit readable/writable up-counter. tcnt is initialized to h'00 by a reset, when the tme bit in tcsr is cleared to 0. 9.2.2 timer control/status register (tcsr) tcsr selects the clock source to be input to tcnt and the timer mode. ? tcsr_0 bit bit name initial value r/w description 7ovf 0 r/(w) * overflow flag indicates that tcnt has overflowed. only a write of 0 is permitted, to clear the flag. [setting condition] when tcnt overflows (changes from h?ff to h?00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing conditions] cleared by reading tcsr when ovf = 1, then writing 0 to ovf 6 wt/it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode 1: watchdog timer mode rev. 0.5, 03/03, page 194 of 438 bit bit name initial value r/w description 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4 3 ? ? 1 1 ? ? reserved these bits are always read as 1 and cannot be modified. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 0 to 2 selects the clock source to be input to tcnt. the overflow frequency for = 20 mhz is enclosed in parentheses. 000: clock /2 (frequency: 25.6 s) 001: clock /64 (frequency: 819.2 s) 010: clock /128 (frequency: 1.6 ms) 011: clock /512 (frequency: 6.6 ms) 100: clock /2048 (frequency: 26.2 ms) 101: clock /8192 (frequency: 104.9 ms) 110: clock /32768 (frequency: 419.4 ms) 111: clock /131072 (frequency: 1.68 s) note: * only 0 can be written, for flag clearing. rev. 0.5, 03/03, page 195 of 438 ? tcsr_1 bit bit name initial value r/w description 7ovf 0 r/(w) * overflow flag indicates that tcnt has overflowed from h?ff to h?00. only a write of 0 is permitted, to clear the flag. [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. [clearing condition] cleared by reading tcsr when ovf = 1, then writing 0 to ovf 6wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. 0: interval timer mode 1: watchdog timer mode 5 tme 0 r/w timer enable when this bit is set to 1, tcnt starts counting. when this bit is cleared, tcnt stops counting and is initialized to h'00. 4 pss 0 r/w prescaler select selects the clock source to be input to tcnt. 0: counts the divided clock of ?based prescaler (psm) 1: counts the divided clock of sub?based prescaler (pss) 3 rst/nmi 0 r/w reset or nmi selects whether an internal reset request or an nmi interrupt request when the tcnt overflows during the watchdog timer mode. 0: nmi interrupt request 1: internal reset request rev. 0.5, 03/03, page 196 of 438 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 selects the clock source to be input to tcnt. the overflow cycle is the period from which tcnt starts incrementing at h 00 and until it overflows. when pss = 0 (values in parentheses are for = 20 mhz): 000: /2 (cycle: 25.6 s) 001: /64 (cycle: 819.2 ms) 010: /128 (cycle: 1.6 ms) 011: /512 (cycle: 6.6 ms) 100: /2048 (cycle: 26.2 ms) 101: /8192 (cycle: 104.9 ms) 110: /32768 (cycle: 419.4 ms) 111: /131072 (cycle: 1.68 s) when pss = 1 (values in parentheses are for sub = 32.768 khz): 000: sub/2 (cycle: 13.1 ms) 001: sub/4 (cycle: 26.2 ms) 010: sub/8 (cycle: 52.4 ms) 011: sub/16 (cycle: 104.9 ms) 100: sub/32 (cycle: 209.7 ms) 101: sub/64 (cycle: 419.4 ms) 110: sub/128 (cycle: 838.9 ms) 111: sub/256 (cycle: 1.6777 s) note: * only 0 can be written, for flag clearing. rev. 0.5, 03/03, page 197 of 438 9.2.3 reset control/status register (rstcsr) rstcsr controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, and not by the wdt internal reset signal caused by overflows. bit bit name initial value r/w description 7wovf0 r/(w) * watchdog overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode, and only 0 can be written. [setting condition] set when tcnt overflows (changed from h'ff to h'00) in watchdog timer mode [clearing condition] cleared by reading rstcsr when wovf = 1, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not a reset signal is generated in the chip if tcnt overflows during watchdog timer operation. 0: reset signal is not generated even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: reset signal is generated if tcnt overflows 5 rsts 0 r/w reset select selects the type of internal reset generated if tcnt overflows during watchdog timer operation. 0: power-on reset 1: setting prohibited 4 to 0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. note: * only 0 can be written, for flag clearing. rev. 0.5, 03/03, page 198 of 438 9.3 operation 9.3.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it bit in tcsr and the tme bit to 1. tcnt does not overflow while the system is operating normally. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. when the wdt is used as a watchdog timer, and if tcnt overflows without being rewritten because of a system malfunction or other error, a wdtovf signal is output when using the wdt_0. in watchdog timer mode, the wdt can internally reset this lsi with a wdtovf signal. when the rste bit of the rstcsr is set to 1, and if the tcnt overflows, an internal reset signal for this lsi is issued at the same time as a wdtovf signal. in this case, select power-on reset by setting the rsts bit in rstcsr to 0. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. the wdtovf signal is output for 132 states when the rste bit = 1 in rstcsr, and for 130 states when the rste bit = 0. the internal reset signal is output for 518 states. this is illustrated in figure 9.3 (a). when the tcnt overflows in watchdog timer mode, the wovf bit in rstcsr is set to 1. if the rste bit in rstcsr has been set to 1, an internal reset signal for the entire lsi is generated at tcnt overflow. in the case of the wdt_1, the chip is reset, or an nmi interrupt request is generated, for 516 system clock periods (516 ) (515 or 516 states when the clock source is sub (pss = 1)). this is illustrated in figure 9.3 (b). an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin are both treated as having the same vector. so, avoid handling an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin at the same time. rev. 0.5, 03/03, page 199 of 438 tcnt value h'00 time h'ff wt/ = 1 tme = 1 write h'00 to tcnt wt/ = 1 tme = 1 write h'00 to tcnt 518 states internal reset signal * wt/ tme notes: 1. 2. after the wovf bit becomes 1, it is cleared to 0 by an internal reset. the internal reset signal is generated only if the rste bit is set to 1. overflow internal reset is generated wovf = 1 * : timer mode select bit : timer enable bit legend 2 1 figure 9.3 (a) wdt_0 operation in watchdog timer mode tcnt value h'00 time h'ff wt/it = 1 tme = 1 write h'00 to tcnt wt/it = 1 tme = 1 write h'00 to tcnt 515/516 states wt/it tme legend overflow internal reset is generated wovf = 1 * : timer mode select bit : timer enable bit 1 internal reset signal * 2 notes: 1. 2. after the wovf bit becomes 1, it is cleared to 0 by an internal reset. the internal reset signal is generated only if the rste bit is set to 1. figure 9.3 (b) wdt_1 operation in watchdog timer mode rev. 0.5, 03/03, page 200 of 438 9.3.2 interval timer mode when the wdt is used as an interval timer, an interval timer interrupt (wovi) is generated each time the tcnt overflows. therefore, an interrupt can be generated at intervals. when the tcnt overflows in interval timer mode, an interval timer interrupt (wovi) is requested at the time the ovf bit of the tcsr is set to 1. 9.4 interrupt sources during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. if an nmi interrupt request has been selected in watchdog timer mode, an nmi interrupt request is generated when the tcnt overflows. table 9.1 wdt interrupt sources name interrupt source interrupt flag wovi tcnt overflow (interval timer mode) ovf nmi tcnt overflow (watchdog timer mode) ovf 9.5 usage notes 9.5.1 notes on register access the watchdog timer?s tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt, tcsr, and rstcsr these registers must be written to by a word transfer instruction. they cannot be written to by a byte transfer instruction. tcnt and tcsr both have the same write address. therefore, the relative condition shown in figure 9.3 needs to be satisfied in order to write to tcnt or tcsr. the transfer instruction writes the lower byte data to tcnt or tcsr according to the satisfied condition. to write to rstcsr, execute a word transfer instruction for address h'ff76. a byte transfer instruction cannot write to rstcsr. rev. 0.5, 03/03, page 201 of 438 the method of writing 0 to the wovf bit differs from that of writing to the rste and rsts bits. to write 0 to the wovf bit, satisfy the condition shown in figure 9.4. if satisfied, the transfer instruction clears the wovf bit to 0, but has no effect on the rste and rsts bits. to write to the rste and rsts bits, satisfy the condition shown in figure 9.4. if satisfied, the transfer instruction writes the values in bits 5 and 6 of the lower byte into the rste and rsts bits, respectively, but has no effect on the wovf bit. tcnt write writing to rste and rsts bits tcsr write writing 0 to wovf bit address: address: 15 8 7 0 h'5a h'ff74 h'ff76 write data 15 8 7 0 h'a5 h'ff74 h'ff76 write data or h'00 figure 9.4 writing to tcnt, tcsr, and rstcsr (example for wdt0) reading tcnt, tcsr, and rstcsr (wdt0) these registers are read in the same way as other registers. the read addresses are h'ff74 for tcsr, h'ff75 for tcnt, and h'ff77 for rstcsr. 9.5.2 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 9.5 shows this operation. address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 9.5 contention between tcnt write and increment rev. 0.5, 03/03, page 202 of 438 9.5.3 changing value of cks2 to cks0 if bits cks0 to cks2 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must be used to stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks0 to cks2. 9.5.4 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer while the wdt is operating, errors could occur in the incrementation. software must be used to stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 9.5.5 internal reset in watchdog timer mode this lsi is not reset internally if tcnt overflows while the rste bit is cleared to 0 during watchdog timer operation, however tcnt and tcsr of the wdt are reset. tcnt, tcsr, or rstcr cannot be written to for 132 states following an overflow. during this period, any attempt to read the wovf flag is not acknowledged. accordingly, wait 132 states after overflow to write 0 to the wovf flag for clearing. 9.5.6 ovf flag clearing in interval timer mode when the ovf flag setting conflicts with the ovf flag reading in interval timer mode, writing 0 to the ovf bit may not clear the flag even though the ovf bit has been read while it is 1. if there is a possibility that the ovf flag setting and reading will conflict, such as when the ovf flag is polled with the interval timer interrupt disabled, read the ovf bit while it is 1 at least twice before writing 0 to the ovf bit to clear the flag. sci0000a_000020020200 rev.0.5, 03/03, page 203 of 438 section 10 serial communication interface (sci) this lsi has three independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). the sci also supports an ic card (smart card) interface conforming to iso/iec 7816-3 (identification card) as a serial communication interface extension function. figure 10.1 shows a block diagram of the sci. 10.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected external clock can be selected as a transfer clock source (except for in smart card interface mode). ? choice of lsb-first or msb-first transfer (except in the case of asynchronous mode 7-bit data) ? four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error ? that can issue requests. ? module stop mode can be set asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity, overrun, and framing errors ? break detection: break can be detected by reading the rxd pin level directly in the case of a framing error rev. 0.5, 03/03, page 204 of 438 clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected smart card interface ? automatic transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported rxd txd sck clock external clock ? ?/4 ?/16 ?/64 tei txi rxi eri rsr rdr tsr tdr smr scr ssr scmr brr : receive shift register : receive data register : transmit shift register : transmit data register : serial mode register : serial control register : serial status register : smart card mode register : bit rate register scmr ssr scr smr transmission/ reception control baud rate generator brr module data bus bus interface rdr tsr rsr parity generation parity check legend tdr internal data bus figure 10.1 block diagram of sci rev.0.5, 03/03, page 205 of 438 10.2 input/output pins table 10.1 shows the serial pins for each sci channel. table 10.1 pin configuration channel pin name * i/o function sck0 i/o sci0 clock input/output rxd0 input sci0 receive data input 0 txd0 output sci0 transmit data output sck1 i/o sci1 clock input/output rxd1 input sci1 receive data input 1 txd1 output sci1 transmit data output sck2 i/o sci2 clock input/output rxd2 input sci2 receive data input 2 txd2 output sci2 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 10.3 register descriptions the sci has the following registers for each channel. the serial mode register (smr), serial status register (ssr), and serial control register (scr) are described separately for normal serial communication interface mode and smart card interface mode because their bit functions differ in part. ? receive shift register (rsr) ? receive data register (rdr) ? transmit data register (tdr) ? transmit shift register (tsr) ? serial mode register (smr) ? serial control register (scr) ? serial status register (ssr) ? smart card mode register (scmr) ? bit rate register (brr) rev. 0.5, 03/03, page 206 of 438 10.3.1 receive shift register (rsr) rsr is a shift register that is used to receive serial data input to the rxd pin and convert it into parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 10.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a double buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. 10.3.3 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double-buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during serial transmission, the sci transfers the written data to tsr to continue transmission. although tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr only once after confirming that the tdre bit in ssr is set to 1. 10.3.4 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. rev.0.5, 03/03, page 207 of 438 10.3.5 serial mode register (smr) smr is used to set the sci?s serial transfer format and select the baud rate generator clock source. some bit functions of smr differ between normal serial communication interface mode and smart card interface mode. normal serial communication interface mode (when smif in scmr is 0): bit bit name initial value r/w description 7c/ a 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb of tdr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 4o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is treated as the start bit of the next transmit character. rev. 0.5, 03/03, page 208 of 438 bit bit name initial value r/w description 2 mp 0 r/w multiprocessor mode (enabled only in asynchronous mode) when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode. 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1: these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 10.3.9, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 10.3.9, bit rate register (brr)). smart card interface mode (when smif in scmr is 1): bit bit name initial value r/w description 7 gm 0 r/w gsm mode when this bit is set to 1, the sci operates in gsm mode. in gsm mode, the timing of the tend setting is advanced by 11.0 etu (elementary time unit: the time for transfer of one bit), and clock output control mode addition is performed. for details, refer to section 10.7.8, clock output control. 6 blk 0 r/w when this bit is set to 1, the sci operates in block transfer mode. for details on block transfer mode, refer to section 10.7.3, block transfer mode. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. in smart card interface mode, this bit must be set to 1. rev.0.5, 03/03, page 209 of 438 bit bit name initial value r/w description 4o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. for details on setting this bit in smart card interface mode, refer to section 10.7.2, data format (except for block transfer mode). 3 2 bcp1 bcp0 0 0 r/w r/w basic clock pulse 1 and 2 these bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. 00: 32 clock (s = 32) 01: 64 clock (s = 64) 10: 372 clock (s = 372) 11: 256 clock (s = 256) for details, refer to section 10.7.4, receive data sampling timing and reception margin in smart card interface mode. s stands for the value of s in brr (see section 10.3.9, bit rate register (brr)). 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 10.3.9, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 10.3.9, bit rate register (brr)). rev. 0.5, 03/03, page 210 of 438 10.3.6 serial control register (scr) scr is a register that enables or disables sci transfer operations and interrupt requests, and is also used to selection of the transfer clock source. for details on interrupt requests, refer to section 10.8, interrupt sources. some bit functions of scr differ between normal serial communication interface mode and smart card interface mode. normal serial communication interface mode (when smif in scmr is 0): bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 10.5, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable this bit is set to 1, tei interrupt request is enabled. rev.0.5, 03/03, page 211 of 438 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source and sck pin function. asynchronous mode 00: internal clock sck pin functions as i/o port 01: internal clock outputs a clock of the same frequency as the bit rate from the sck pin. 1x: external clock inputs a clock with a frequency 16 times the bit rate from the sck pin. clocked synchronous mode 0x: internal clock (sck pin functions as clock output) 1x: external clock (sck pin functions as clock input) legend x: don?t care smart card interface mode (when smif in scmr is 1): bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) write 0 to this bit in smart card interface mode. 2 teie 0 r/w transmit end interrupt enable write 0 to this bit in smart card interface mode. rev. 0.5, 03/03, page 212 of 438 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w clock enable 0 and 1 enables or disables clock output from the sck pin. the clock output can be dynamically switched in gsm mode. for details, refer to section 10.7.8, clock output control. when the gm bit in smr is 0: 00: output disabled (sck pin can be used as an i/o port pin) 01: clock output 1x: reserved when the gm bit in smr is 1: 00: output fixed low 01: clock output 10: output fixed high 11: clock output legend x: don?t care 10.3.7 serial status register (ssr) ssr is a register containing status flags of the sci and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, orer, per, and fer; they can only be cleared. some bit functions of ssr differ between normal serial communication interface mode and smart card interface mode. normal serial communication interface mode (when smif in scmr is 0): bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing condition] ? when 0 is written to tdre after reading tdre = 1 rev.0.5, 03/03, page 213 of 438 bit bit name initial value r/w description 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ? when 0 is written to rdrf after reading rdrf = 1 the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 5 orer 0 r/w overrun error [setting condition] ? when the next serial reception is completed while rdrf = 1 [clearing condition] ? when 0 is written to orer after reading orer = 1 4 fer 0 r/w framing error [setting condition] ? when the stop bit is 0 [clearing condition] ? when 0 is written to fer after reading fer = 1 in 2-stop-bit mode, only the first stop bit is checked. 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 rev. 0.5, 03/03, page 214 of 438 bit bit name initial value r/w description 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing condition] ? when 0 is written to tdre after reading tdre = 1 1 mpb 0 r multiprocessor bit mpb stores the multiprocessor bit in the receive data. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit data. smart card interface mode (when smif in scmr is 1): bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing condition] ? when 0 is written to tdre after reading tdre = 1 rev.0.5, 03/03, page 215 of 438 bit bit name initial value r/w description 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing condition] ? when 0 is written to rdrf after reading rdrf = 1 the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 5 orer 0 r/w overrun error [setting condition] ? when the next serial reception is completed while rdrf = 1 [clearing condition] ? when 0 is written to orer after reading orer = 1 4 ers 0 r/w error signal status [setting condition] ? when the low level of the error signal is sampled [clearing condition] ? when 0 is written to ers after reading ers = 1 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 rev. 0.5, 03/03, page 216 of 438 bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to tdr. [setting conditions] ? when the te bit in scr is 0 and the ers bit is also 0 ? when the esr bit is 0 and the tdre bit is 1 after the specified interval following transmission of 1- byte data. the timing of bit setting differs according to the register setting as follows: when gm = 0 and blk = 0, 2.5 etu after transmission starts when gm = 0 and blk = 1, 1.5 etu after transmission starts when gm = 1 and blk = 0, 1.0 etu after transmission starts when gm = 1 and blk = 1, 1.0 etu after transmission starts [clearing condition] ? when 0 is written to tdre after reading tdre = 1 1 mpb 0 r multiprocessor bit this bit is not used in smart card interface mode. 0 mpbt 0 r/w multiprocessor bit transfer write 0 to this bit in smart card interface mode. rev.0.5, 03/03, page 217 of 438 10.3.8 smart card mode register (scmr) scmr is a register that selects smart card interface mode and its format. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 sdir 0 r/w smart card data transfer direction selects the serial/parallel conversion format. 0: lsb-first in transfer 1: msb-first in transfer the bit setting is valid only when the transfer data format is 8 bits. for 7-bit data, lsb-first is fixed. 2 sinv 0 r/w smart card data invert specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit. to invert the parity bit, invert the o/ e bit in smr. 0: tdr contents are transmitted as they are. receive data is stored as it is in rdr 1: tdr contents are inverted before being transmitted. receive data is stored in inverted form in rdr 1 ? 1 ? reserved this bit is always read as 1. 0 smif 0 r/w smart card interface mode select this bit is set to 1 to make the sci operate in smart card interface mode. 0: normal asynchronous mode or clocked synchronous mode 1: smart card interface mode rev. 0.5, 03/03, page 218 of 438 10.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rates can be set for each channel. table 10.2 shows the relationships between the n setting in brr and bit rate b for normal asynchronous mode, clocked synchronous mode, and smart card interface mode. the initial value of brr is h'ff, and it can be read or written to by the cpu at all times. table 10.2 relationships between n setting in brr and bit rate b mode bit rate error asynchronous mode b = 64 2 2n-1 (n + 1) 10 6 error (%) = { b 64 2 2n-1 (n + 1) -1 } 100 10 6 clocked synchronous mode b = 8 2 2n-1 (n + 1) 10 6 smart card interface mode b = s 2 2n-1 (n + 1) 10 6 error (%) = { b s 2 2n-1 (n + 1) -1 } 100 10 6 note: b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n and s: determined by the smr settings shown in the following tables. smr setting smr setting cks1 cks0 n bcp1 bcp0 s 000 0032 011 0164 102 10372 113 11256 table 10.3 shows sample n settings in brr in normal asynchronous mode. table 10.4 shows the maximum bit rate for each frequency in normal asynchronous mode. table 10.6 shows sample n settings in brr in clocked synchronous mode. table 10.8 shows sample n settings in brr in smart card interface mode. in smart card interface mode, s (the number of basic clock periods in a 1-bit transfer interval) can be selected. for details, refer to section 10.7.4, receive data sampling timing and reception margin. tables 10.5 and 10.7 show the maximum bit rates with external clock input. rev.0.5, 03/03, page 219 of 438 table 10.3 brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 44.91525 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 12 0.16 0 15 0.00 0 15 1.73 19200 ? ? ? 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 ? ? ? 0 3 0.00 0 3 1.73 operating frequency (mhz) 6 6.144 7.3728 8 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 ? ? ? 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 ? ? ? rev. 0.5, 03/03, page 220 of 438 table 10.3 brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 9.8304 10 12 12.288 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00 operating frequency (mhz) 14 14.7456 16 17.2032 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.13 2 191 0.00 2 207 0.13 2 223 0.00 300 2 90 0.13 2 95 0.00 2 103 0.13 2 111 0.00 600 1 181 0.13 1 191 0.00 1 207 0.13 1 223 0.00 1200 1 90 0.13 1 95 0.00 1 103 0.13 1 111 0.00 2400 0 181 0.13 0 191 0.00 0 207 0.13 0 223 0.00 4800 0 90 0.13 0 95 0.00 0 103 0.13 0 111 0.00 9600 0 45 ?0.93 0 47 0.00 0 51 0.13 0 55 0.00 19200 0 22 ?0.93 0 23 0.00 0 25 0.13 0 27 0.00 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 0 13 1.20 38400 ? ? ? 0 11 0.00 0 12 0.13 0 13 0.00 rev.0.5, 03/03, page 221 of 438 table 10.3 brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 18 19.6608 20 24 bit rate (bit/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 3 79 ?0.12 3 86 0.31 3 88 ?0.25 3 106 ?0.44 150 2 233 0.16 2 255 0.00 3 64 0.16 3 77 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 2 155 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 2 77 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 1 155 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 1 77 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 0 155 0.16 9600 0 58 ?0.69 0 63 0.00 0 64 0.16 0 77 0.16 19200 0 28 1.02 0 31 0.00 0 32 ?1.36 0 38 0.16 31250 0 17 0.00 0 19 ?1.70 0 19 0.00 0 23 0.00 38400 0 14 ?2.34 0 15 0.00 0 15 1.73 0 19 ?2.34 table 10.4 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) nn (mhz) maximum bit rate (bit/s) nn 4 125000 0 0 12.288 384000 0 0 4.9152 153600 0 0 14 437500 0 0 5 156250 0 0 14.7456 460800 0 0 6 187500 0 0 16 500000 0 0 6.144 192000 0 0 17.2032 537600 0 0 7.3728 230400 0 0 18 562500 0 0 8 250000 0 0 19.6608 614400 0 0 9.8304 307200 0 0 20 625000 0 0 10 312500 0 0 24 750000 0 0 12 375000 0 0 rev. 0.5, 03/03, page 222 of 438 table 10.5 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) (mhz) external input clock (mhz) maximum bit rate (bit/s) 4 1.0000 62500 12.288 3.0720 192000 4.9152 1.2288 76800 14 3.5000 218750 5 1.2500 78125 14.7456 3.6864 230400 6 1.5000 93750 16 4.0000 250000 6.144 1.5360 96000 17.2032 4.3008 268800 7.3728 1.8432 115200 18 4.5000 281250 8 2.0000 125000 19.6608 4.9152 307200 9.8304 2.4576 153600 20 5.0000 312500 10 2.5000 156250 24 6.0000 375000 12 3.0000 187500 rev.0.5, 03/03, page 223 of 438 table 10.6 brr settings for various bit rates (clocked synchronous mode) operating frequency (mhz) 4 8 10 16 20 24 bit rate (bit/s) n n nn n n nn n n n n 110 ? ? 250 2 249 3 124 ? ? 3 249 500 2 124 2 249 ? ? 3 124 ? ? ? ? 1k 1 249 2 124 ? ? 2 249 ? ? ? ? 2.5k 1 99 1 199 1 249 2 99 2 124 2 149 5k 0 199 1 99 1 124 1 199 1 249 2 74 10k 0 99 0 199 0 249 1 99 1 124 1 149 25k 0 39 0 79 0 99 0 159 0 199 1 59 50k 0 19 0 39 0 49 0 79 0 99 1 29 100k 0 9 0 19 0 24 0 39 0 49 0 59 250k 0 3 0 7 0 9 0 15 0 19 0 23 500k 0 1 0 3 0 4 0 7 0 9 0 11 1m 0 0 * 01 03 0 4 0 5 2.5m 0 0 * 01 ?? 5m 0 0 * ?? legend blank : cannot be set. ? : can be set, but there will be a degree of error. * : continuous transfer is not possible. table 10.7 maximum bit rate with external clock input (clocked synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) (mhz) external input clock (mhz) maximum bit rate (bit/s) 4 0.6667 666666.7 14 2.3333 2333333.3 6 1.0000 1000000.0 16 2.6667 2666666.7 8 1.3333 1333333.3 18 3.0000 3000000.0 10 1.6667 1666666.7 20 3.3333 3333333.3 12 2.0000 2000000.0 24 4.0000 4000000.0 rev. 0.5, 03/03, page 224 of 438 table 10.8 examples of bit rate for various brr settings (smart card interface mode) (when n = 0 and s = 372) operating frequency (mhz) 7.1424 10.00 10.7136 13.00 bit rate (bit/s) n n error (%) nn error (%) nn error (%) nn error (%) 9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99 operating frequency (mhz) 14.2848 16.00 18.00 20.00 24.00 bit rate (bit/s) n n error (%) nn error (%) nn error (%) nn error (%) nn error (%) 9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60 0 2 12.01 table 10.9 maximum bit rate at various frequencies (smart card interface mode) (when s = 372) (mhz) maximum bit rate (bit/s) nn (mhz) maximum bit rate (bit/s) nn 7.1424 9600 0 0 16.00 21505 0 0 10.00 13441 0 0 18.00 24194 0 0 10.7136 14400 0 0 20.00 26882 0 0 13.00 17473 0 0 24.00 32258 0 0 14.2848 19200 0 0 rev.0.5, 03/03, page 225 of 438 10.4 operation in asynchronous mode figure 10.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line. when the transmission line goes to the space state (low level), the sci recognizes a start bit and starts serial communication. in asynchronous serial communication, the communication line is usually held in the mark state (high level). the sci monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 10.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 10.4.1 data transfer format table 10.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, refer to section 10.5, multiprocessor communication function. rev. 0.5, 03/03, page 226 of 438 table 10.10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 ? ? ? ? s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend s : start bit stop : stop bit p: parity bit mpb : multiprocessor bit rev.0.5, 03/03, page 227 of 438 10.4.2 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.3. thus, the reception margin in asynchronous mode is given by formula (1) below. m = { (0.5 ? ) ? ? (l ? 0.5) f} 100 [%] 1 2n d ? 0.5 n ... formula (1) where m : reception margin n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0.5 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 10.3 receive data sampling timing in asynchronous mode rev. 0.5, 03/03, page 228 of 438 10.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci?s serial clock, according to the setting of the c/ a bit in smr and the cke0 and cke1 bits in scr. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.4. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 sck txd figure 10.4 relationship between output clock and transfer data phase (asynchronous mode) rev.0.5, 03/03, page 229 of 438 10.4.4 sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait rev. 0.5, 03/03, page 230 of 438 10.4.5 data transmission (asynchronous mode) figure 10.6 shows an example of operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr. if the flag is cleared to 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 10.7 shows a sample flowchart for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 10.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) rev.0.5, 03/03, page 231 of 438 no rev. 0.5, 03/03, page 232 of 438 10.4.6 serial data reception (asynchronous mode) figure 10.8 shows an example of operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line. if a start bit is detected, the sci performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has been completed. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated figure 10.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit) rev.0.5, 03/03, page 233 of 438 table 10.11 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 10.9 shows a sample flow chart for serial data reception. table 10.11 ssr status flags and receive data handling ssr status flag rdrf * orer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception. rev. 0.5, 03/03, page 234 of 438 yes rev.0.5, 03/03, page 235 of 438 rev. 0.5, 03/03, page 236 of 438 10.5 multiprocessor communication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is performed, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles; an id transmission cycle that specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 10.10 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose ids do not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and orer to 1, are inhibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpb bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. rev.0.5, 03/03, page 237 of 438 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend mpb: multiprocessor bit figure 10.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a) rev. 0.5, 03/03, page 238 of 438 10.5.1 multiprocessor serial data transmission figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt bit in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no rev.0.5, 03/03, page 239 of 438 10.5.2 multiprocessor serial data reception figure 10.13 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is transferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 10.12 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit data (id2) start bit stop bit start bit data (data2) stop bit rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this station ? s id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station ? s id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this station ? s id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches station ? s id data2 id1 mpie = 0 mpie = 0 figure 10.12 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) rev. 0.5, 03/03, page 240 of 438 yes rev.0.5, 03/03, page 241 of 438 rev. 0.5, 03/03, page 242 of 438 10.6 operation in clocked synchronous mode figure 10.14 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sci receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. don ? t care don ? t care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 10.14 data format in synchronous communication (for lsb-first) 10.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of cke0 and cke1 bits in scr. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. rev.0.5, 03/03, page 243 of 438 10.6.2 sci initialization (clocked synchronous mode) before transmitting and receiving data, the te and re bits in scr should be cleared to 0, then the sci should be initialized as described in a sample flowchart in figure 10.15. when the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. wait rev. 0.5, 03/03, page 244 of 438 10.6.3 serial data transmission (clocked synchronous mode) figure 10.16 shows an example of sci operation for transmission in clocked synchronous mode. in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if the flag is 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. continuous transmission is possible because the txi interrupt routine writes the next transmit data to tdr before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 10.17 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (orer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. rev.0.5, 03/03, page 245 of 438 transfer direction bit 0 serial data synchronization clock 1 frame tdre tend data written to tdr and tdre flag cleared to 0 in txi interrupt service routine txi interrupt request generated bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request generated tei interrupt request generated figure 10.16 sample sci transmission operation in clocked synchronous mode rev. 0.5, 03/03, page 246 of 438 no rev.0.5, 03/03, page 247 of 438 10.6.4 serial data reception (clocked synchronous mode) figure 10.18 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in rsr. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated, receive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 3. if reception is completed successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has finished. bit 7 serial data synchronization clock 1 frame rdrf orer eri interrupt request generated by overrun error rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 figure 10.18 example of sci operation in reception reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 10.19 shows a sample flow chart for serial data reception. rev. 0.5, 03/03, page 248 of 438 yes rev.0.5, 03/03, page 249 of 438 10.6.5 simultaneous serial data transmission and reception (clocked synchronous mode) figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode, after checking that the sci has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (orer, fer, and per) are cleared to 0, simultaneously set te and re to 1 with a single instruction. rev. 0.5, 03/03, page 250 of 438 yes rev.0.5, 03/03, page 251 of 438 10.7 operation in smart card interface the sci supports an ic card (smart card) interface that conforms to iso/iec 7816-3 (identification card) as a serial communication interface extension function. switching between the normal serial communication interface and the smart card interface mode is carried out by means of a register setting. 10.7.1 pin connection example figure 10.21 shows an example of connection with the smart card. in communication with an ic card, as both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected to the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. this lsi port output is used as the reset signal. txd rxd this lsi v cc i/o connected equipment ic card data line clock line reset line clk rst sck rx (port) figure 10.21 schematic diagram of smart card interface pin connections rev. 0.5, 03/03, page 252 of 438 10.7.2 data format (except for block transfer mode) figure 10.22 shows the transfer data format in smart card interface mode. ? one frame consists of 8-bit data plus a parity bit in asynchronous mode. ? in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output : start bit : data bits : parity bit : error signal legend ds d0 to d7 dp de figure 10.22 normal smart card interface data format data transfer with other types of ic cards (direct convention and inverse convention) are performed as described in the following. ds azzazz z za a (z) (z) state d0 d1 d2 d3 d4 d5 d6 d7 dp figure 10.23 direct convention (sdir = sinv = o/ e e e e = 0) rev.0.5, 03/03, page 253 of 438 with the direction convention type ic and the above sample start character, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. for the direct convention type, clear the sdir and sinv bits in scmr to 0. according to smart card regulations, clear the o/ e bit in smr to 0 to select even parity mode. ds azzaaa z aa a (z) (z) state d7 d6 d5 d4 d3 d2 d1 d0 dp figure 10.24 inverse convention (sdir = sinv = o/ e e e e = 1) with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data for the above is h'3f. for the inverse convention type, set the sdir and sinv bits in scmr to 1. according to smart card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state z. in this lsi, the sinv bit inverts only data bits d0 to d7. therefore, set the o/ e bit in smr to 1 to invert the parity bit for both transmission and reception. 10.7.3 block transfer mode operation in block transfer mode is the same as that in sci asynchronous mode, except for the following points. ? in reception, though the parity check is performed, no error signal is output even if an error is detected. however, the per bit in ssr is set to 1 and must be cleared before receiving the parity bit of the next frame. ? in transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. ? in transmission, because retransmission is not performed, the tend flag is set to 1, 11.5 etu after transmission start. ? as with the normal smart card interface, the ers flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. rev. 0.5, 03/03, page 254 of 438 10.7.4 receive data sampling timing and reception margin in smart card interface mode in smart card interface mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits bcp1 and bcp0. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. as shown in figure 10.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. the reception margin is given by the following formula. m = | (0.5 ? ) ? (l ? 0.5) f ? (1 + f) | 100% 1 2n | d ? 0.5 | n where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5 and n = 372 in the above formula, the reception margin formula is as follows. m = (0.5 ? 1/2 372) 100% = 49.866% internal basic clock 372 clocks 186 clocks receive data (rxd) synchronization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 10.25 receive data sampling timing in smart card interface mode (using clock of 372 times the transfer rate) rev.0.5, 03/03, page 255 of 438 10.7.5 initialization before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. clear the te and re bits in scr to 0. 2. clear the error flags ers, per, and orer in ssr to 0. 3. set the gm, blk, o/ e , bcp0, bcp1, cks0, cks1 bits in smr. set the pe bit to 1. 4. set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. 5. set the value corresponding to the bit rate in brr. 6. set the cke0 and cke1 bits in scr. clear the tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. 7. wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis. to switch from receive mode to transmit mode, after checking that the sci has finished reception, initialize the sci, and set re to 0 and te to 1. whether sci has finished reception or not can be checked with the rdrf, per, or orer flags. to switch from transmit mode to receive mode, after checking that the sci has finished transmission, initialize the sci, and set te to 0 and re to 1. whether sci has finished transmission or not can be checked with the tend flag. 10.7.6 data transmission (except for block transfer mode) as data transmission in smart card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). figure 10.26 illustrates the retransfer operation when the sci is in transmit mode. 1. if an error signal is sent back from the receiving end after transmission of one frame is complete, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the ers bit in ssr should be kept cleared to 0 until the next parity bit is sampled. 2. the tend bit in ssr is not set for a frame in which an error signal indicating an abnormality is received. data is retransferred from tdr to tsr, and retransmitted automatically. 3. if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. writing transmit data to tdr transfers the next transmit data. rev. 0.5, 03/03, page 256 of 438 figure 10.28 shows a flowchart for transmission. in the event of an error in transmission, the sci retransmits the same data automatically. during this period, the tend flag remains cleared to 0. therefore, the sci will automatically transmit the specified number of bytes in the event of an error, including retransmission. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend [6] fer/ers transfer to tsr from tdr transfer to tsr from tdr transfer to tsr from tdr [7] [9] [8] figure 10.26 retransfer operation in sci transmit mode the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 10.27. ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5etu txi (tend interrupt) 11.0etu de guard time when gm = 0 when gm = 1 : start bit : data bits : parity bit : error signal legend ds d0 to d7 dp de figure 10.27 tend flag generation timing in transmission operation rev.0.5, 03/03, page 257 of 438 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre flag in ssr to 0 error processing error processing tend = 1? all data transmitted ? tend = 1? ers = 0? ers = 0? figure 10.28 example of transmission processing flow rev. 0.5, 03/03, page 258 of 438 10.7.7 serial data reception (except for block transfer mode) data reception in smart card interface mode uses the same operation procedure as for normal serial communication interface mode. figure 10.29 illustrates the retransfer operation when the sci is in receive mode. 1. if an error is found when the received parity bit is checked, the per bit in ssr is automatically set to 1. if the rie bit in scr is set at this time, an eri interrupt request is generated. the per bit in ssr should be kept cleared to 0 until the next parity bit is sampled. 2. the rdrf bit in ssr is not set for a frame in which an error has occurred. 3. if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1, the receive operation is judged to have been completed normally, and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. figure 10.30 shows a flowchart for reception. if an error occurs in receive mode and the orer or per flag is set to 1, a transfer error interrupt (eri) request will be generated. hence, so the error flag must be cleared to 0. even when a parity error occurs in receive mode and the per flag is set to 1, the data that has been received is transferred to rdr and can be read from there. note: for details on receive operations in block transfer mode, refer to section 10.4, operation in asynchronous mode. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame rdrf [1] per [2] [3] [4] figure 10.29 retransfer operation in sci receive mode rev.0.5, 03/03, page 259 of 438 initialization read rdr and clear rdrf flag in ssr to 0 clear re bit to 0 start reception start error processing no no no yes yes orer = 0 and per = 0 rdrf = 1? all data received? yes figure 10.30 example of reception processing flow 10.7.8 clock output control when the gm bit in smr is set to 1, the clock output level can be fixed with bits cke0 and cke1 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 10.31 shows the timing for fixing the clock output level. in this example, gm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled. specified pulse width sck cke0 specified pulse width figure 10.31 timing for fixing clock output level rev. 0.5, 03/03, page 260 of 438 when turning on the power or switching between smart card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. powering on: to secure clock duty from power-on, the following switching procedure should be followed. 1. the initial state is port input and high impedance. use a pull-up resistor or pull-down resistor to fix the potential. 2. fix the sck pin to the specified output level with the cke1 bit in scr. 3. set smr and scmr, and switch to smart card mode operation. 4. set the cke0 bit in scr to 1 to start clock output. when changing from smart card interface mode to software standby mode: 1. set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. 2. write 0 to the te bit and re bit in the serial control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. 3. write 0 to the cke0 bit in scr to halt the clock. 4. wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. 5. make the transition to the software standby state. when returning to smart card interface mode from software standby mode: 1. exit the software standby state. 2. write 1 to the cke0 bit in scr and output the clock. signal generation is started with the normal duty. [1] [2] [3] [4] [5] [7] software standby normal operation normal operation [6] figure 10.32 clock halt and restart procedure rev.0.5, 03/03, page 261 of 438 10.8 interrupt sources 10.8.1 interrupts in normal serial communication interface mode table 10.12 shows the interrupt sources in normal serial communication interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. a tei interrupt is requested when the tend flag is set to 1 and the teie bit is set to 1. if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt has priority for acceptance. however, if the tdre and tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot branch to the tei interrupt routine later. table 10.12 sci interrupt sources channel name interrupt source interrupt flag eri0 receive error orer, fer, per rxi0 receive data full rdrf txi0 transmit data empty tdre 0 tei0 transmission end tend eri1 receive error orer, fer, per rxi1 receive data full rdrf txi1 transmit data empty tdre 1 tei1 transmission end tend eri2 receive error orer, fer, per rxi2 receive data full rdrf txi2 transmit data empty tdre 2 tei2 transmission end tend rev. 0.5, 03/03, page 262 of 438 10.8.2 interrupts in smart card interface mode table 10.13 shows the interrupt sources in smart card interface mode. the transmit end interrupt (tei) request cannot be used in this mode. table 10.13 sci interrupt sources channel name interrupt source interrupt flag eri0 receive error, detection orer, per, ers rxi0 receive data full rdrf 0 txi0 transmit data empty tend eri1 receive error, detection orer, per, ers rxi1 receive data full rdrf 1 txi1 transmit data empty tend eri2 receive error, detection orer, per, ers rxi2 receive data full rdrf 2 txi2 transmit data empty tend in transmit operations, the tdre flag is also set to 1 at the same time as the tend flag in ssr is set, and a txi interrupt is generated. in the event of an error, the sci retransmits the same data automatically. during this period, the tend flag remains cleared to 0. therefore, the sci will automatically transmit the specified number of bytes in the event of an error, including retransmission. however, the ers flag is not cleared automatically when an error occurs. hence, the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. in receive operations, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if an error occurs, an error flag is set but the rdrf flag is not. consequently, an eri interrupt request is sent to the cpu. therefore, the error flag should be cleared. rev.0.5, 03/03, page 263 of 438 10.9 usage notes 10.9.1 module stop mode setting sci operation can be disabled or enabled using the module stop control register. the initial setting is for sci operation to be halted. register access is enabled by clearing module stop mode. for details, refer to section 16, power-down modes. 10.9.2 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, setting the fer flag, and possibly the per flag. note that as the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 10.9.3 mark state and break detection when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by dr and ddr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 10.9.4 receive error flags and transmit operations (clocked synchronous mode only) transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. rev. 0.5, 03/03, page 264 of 438 ifcan00b_000120020200 rev. 0.5, 03/03, page 265 of 438 section 11 hitachi controller area network (hcan) the hcan is a module for controlling a controller area network (can) for realtime communication in vehicular and industrial equipment systems, etc. for details on can specification, refer to bosch can specification version 2.0 1991, robert bosch gmbh. the block diagram of the hcan is shown in figure 11.1. 11.1 features ? can version: bosch 2.0b active compatible ? communication systems: nrz (non-return to zero) system (with bit-stuffing function) ? broadcast communication system ? transmission path: bidirectional 2-wire serial communication ? communication speed: max. 1 mbps ? data length: 0 to 8 bytes ? number of channels: 1 ? data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) ? data transmission: two methods ? mailbox (buffer) number order (low-to-high) ? message priority (identifier) reverse-order (high-to-low) ? data reception: two methods ? message identifier match (transmit/receive-setting buffers) ? reception with message identifier masked (receive-only) ? cpu interrupts: 12 ? error interrupt ? reset processing interrupt ? message reception interrupt ? message transmission interrupt ? hcan operating modes ? support for various modes ? hardware reset ? software reset ? normal status (error-active, error-passive) ? bus off status ? hcan configuration mode ? hcan sleep mode ? hcan halt mode rev. 0.5, 03/03, page 266 of 438 ? module stop mode can be set peripheral address bus peripheral data bus htxd mbi hrxd can data link controller mpi (cdlc) tx buffer rx buffer message buffer message control message data mc0?mc15, md0?md15 lafm mailboxes microprocessor interface cpu interface control register status register hcan bosch can 2.0b active figure 11.1 hcan block diagram ? message buffer interface (mbi) the mbi, consisting of mailboxes and a local acceptance filter mask (lafm), stores can transmit/receive messages (identifiers, data, etc.) transmit messages are written by the cpu. for receive messages, the data received by the cdlc is stored automatically. ? microprocessor interface (mpi) the mpi, consisting of a bus interface, control register, status register, etc., controls hcan internal data, status, and so forth. ? can data link controller (cdlc) the cdlc transmits and receives of messages conforming to the bosch can ver. 2.0b active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as crc checking, bus arbitration, and other functions. rev. 0.5, 03/03, page 267 of 438 11.2 input/output pins table 11.1 shows the hcan's pins. when using hcan pins, settings must be made in the hcan configuration mode (during initialization: mcr0 = 1 and gsr3 = 1). table 11.1 pin configuration name abbreviation input/output function hcan transmit data pin htxd output can bus transmission pin hcan receive data pin hrxd input can bus reception pin a bus driver is necessary for the interface between the pins and the can bus. a philips pca82c250 compatible model is recommended. 11.3 register descriptions the hcan has the following registers. ? master control register (mcr) ? general status register (gsr) ? bit configuration register (bcr) ? mailbox configuration register (mbcr) ? transmit wait register (txpr) ? transmit wait cancel register (txcr) ? transmit acknowledge register (txack) ? abort acknowledge register (aback) ? receive complete register (rxpr) ? remote request register (rfpr) ? interrupt register (irr) ? mailbox interrupt mask register (mbimr) ? interrupt mask register (imr) ? receive error counter (rec) ? transmit error counter (tec) ? unread message status register (umsr) ? local acceptance filter mask h (lafmh) ? local acceptance filter mask l (lafml) ? message control (8-bit 8 registers 16 sets) (mc0 to mc15) ? message data (8-bit 8 registers 16 sets) (md0 to md15) rev. 0.5, 03/03, page 268 of 438 ? hcan monitor register (hcanmon) 11.3.1 master control register (mcr) mcr controls the hcan. bit bit name initial value r/w description 7 mcr7 0 r/w hcan sleep mode release when this bit is set to 1, the hcan automatically exits hcan sleep mode on detection of can bus operation. 6 ? 0rreserved this bit is always read as 0. only 0 should be written to this bit. 5 mcr5 0 r/w hcan sleep mode when this bit is set to 1, the hcan transits to hcan sleep mode. when this bit is cleared to 0, hcan sleep mode is released. 4 3 ? ? 0 0 r r reserved these bits are always read as 0. only 0 should be written to these bits. 2 mcr2 0 r/w message transmission method 0: transmission order determined by message identifier priority 1: transmission order determined by mailbox (buffer) number priority (txpr1 > txpr15) 1 mcr1 0 r/w halt request when this bit is set to 1, the hcan transits to hcan halt mode. when this bit is cleared to 0, hcan halt mode is released. rev. 0.5, 03/03, page 269 of 438 bit bit name initial value r/w description 0 mcr0 1 r/w reset request when this bit is set to 1, the hcan transits to reset mode. for details, refer to section 11.4.1, hardware and software resets. [setting conditions] ? power-on reset ? hardware standby ? software standby ? 1-write (software reset) [clearing condition] ? when 0 is written to this bit while the gsr3 bit in gsr is 1 11.3.2 general status register (gsr) gsr indicates the status of the hcan. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits. 3 gsr3 1 r reset status bit indicates whether the hcan module is in the normal operating state or the reset state. this bit cannot be modified. [setting condition] ? when entering configuration mode after the hcan internal reset has finished ? sleep mode [clearing condition] ? when entering normal operation mode after the mcr0 bit in mcr is cleared to 0 (note that there is a delay between clearing of the mcr0 bit and the gsr3 bit.) rev. 0.5, 03/03, page 270 of 438 bit bit name initial value r/w description 2 gsr2 1 r message transmission status flag flag that indicates whether the module is currently in the message transmission period. this bit cannot be modified. [setting condition] ? start of message transmission (sof) [clearing condition] ? interval of three bits after eof (end of frame) 1 gsr1 0 r transmit/receive warning flag this bit cannot be modified. [clearing condition] ? when tec < 96 and rec < 96 or tec 256 [setting condition] ? when tec 96 or rec 96 0 gsr0 0 r bus off flag this bit cannot be modified. [setting condition] ? when tec 256 (bus off state) [clearing condition] ? recovery from bus off state rev. 0.5, 03/03, page 271 of 438 11.3.3 bit configuration register (bcr) bcr sets hcan bit timing parameters and the baud rate prescaler. for details on parameters, refer to section 11.4.2, initialization after hardware reset. bit bit name initial value r/w description 15 14 bcr7 bcr6 0 0 r/w r/w re-synchronization jump width (sjw) set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 13 12 11 10 9 8 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w baud rate prescaler (brp) set the length of time quantum. 000000: 2 system clock 000001: 4 system clock 000010: 6 system clock : 111111: 128 system clock 7 bcr15 0 r/w bit sample point (bsp) sets the point at which data is sampled. 0: bit sampling at one point (end of time segment 1 (tseg1)) 1: bit sampling at three points (end of tseg1 and preceding and following one time quantum) 6 5 4 bcr14 bcr13 bcr12 0 0 0 r/w r/w r/w time segment 2 (tseg2) set the tseg2 width within a range of 2 to 8 time quanta. 000: setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta rev. 0.5, 03/03, page 272 of 438 bit bit name initial value r/w description 3 2 1 0 bcr11 bcr10 bcr9 bcr8 0 0 0 0 r/w r/w r/w r/w time segment 1 (tseg1) set the tseg1 (prseg + phseg1) width to between 4 and 16 time quanta. 0000: setting prohibited 0001: setting prohibited 0010: setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta rev. 0.5, 03/03, page 273 of 438 11.3.4 mailbox configuration register (mbcr) mbcr sets the transfer direction for each mailbox. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits set the transfer direction for the corresponding mailboxes from 1 to 15. mbcrn determines the transfer direction for mailbox n (n = 1 to 15). 0: corresponding mailbox is set for transmission 1: corresponding mailbox is set for reception bit 8 is reserved. this bit is always read as 1 and the write value should always be 1. rev. 0.5, 03/03, page 274 of 438 11.3.5 transmit wait register (txpr) txpr sets a transmit wait after a transmit message is stored in a mailbox (buffer) (can bus arbitration wait). bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? txpr15 txpr14 txpr13 txpr12 txpr11 txpr10 txpr9 txpr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits set a transmit wait (can bus arbitration wait) for the corresponding mailboxes 1 to 15. when txprn (n = 1 to 15) is set to 1, the message in mailbox n becomes the transmit wait state. [clearing condition] ? completion of message transmission ? completion of transmission cancellation bit 8 is reserved. this bit is always read as 1 and the write value should always be 1. rev. 0.5, 03/03, page 275 of 438 11.3.6 transmit wait cancel register (txcr) txcr controls canceling transmission of transmit wait messages in mailboxes (buffers). bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. when txcrn (n = 1 to 15) is set to 1, the transmit wait message in mailbox n is canceled. [clearing condition] ? completion of txpr clearing when transmit message is canceled normally bit 8 is reserved. this bit is always read as 0 and the write value should always be 0. rev. 0.5, 03/03, page 276 of 438 11.3.7 transmit acknowledge register (txack) txack is a status register that indicates the normal transmission of mailbox (buffer) transmit messages. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? txack15 txack14 txack13 txack12 txack11 txack10 txack9 txack8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w these bits are status flags that indicate error-free transmission of the transmit message in the corresponding mailboxes 1 to 15. when the message in mailbox n (n = 1 to 15) has been transmitted error- free, txackn is set to 1. [setting condition] ? completion of message transmission for corresponding mailbox [clearing condition] ? writing 1 bit 8 is reserved. this bit is always read as 0 and the write value should always be 0. rev. 0.5, 03/03, page 277 of 438 11.3.8 abort acknowledge register (aback) aback is a status register that indicates the normal cancellation (aborting) of mailbox (buffer) transmit messages. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * these bits are status flags that indicate error-free cancellation (abortion) of the transmit message in the corresponding mailboxes 1 to 15. when the message in mailbox n (n = 1 to 15) has been canceled error- free, abackn is set to 1. [setting condition] ? completion of transmit message cancellation for corresponding mailbox [clearing condition] ? writing 1 bit 8 is reserved. this bit is always read as 0. the write value should always be 0. note: * only 1 can be written for clearing the flag. rev. 0.5, 03/03, page 278 of 438 11.3.9 receive complete register (rxpr) rxpr is a status register that indicates the normal reception of messages (data frame or remote frame) in mailboxes (buffers). for reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (rfpr) bit is also set to 1 simultaneously. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxpr7 rxpr6 rxpr5 rxpr4 rxpr3 rxpr2 rxpr1 rxpr0 rxpr15 rxpr14 rxpr13 rxpr12 rxpr11 rxpr10 rxpr9 rxpr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * when the message in mailbox n (n = 0 to 15) has been received error-free, rxprn is set to 1. [setting condition] ? completion of message (data frame or remote frame) reception in corresponding mailbox [clearing condition] ? writing 1 note: * only 1 can be written for clearing the flag. rev. 0.5, 03/03, page 279 of 438 11.3.10 remote request register (rfpr) rfpr is a status register that indicates normal reception of remote frames in mailboxes (buffers). when a bit in this register is set to 1, the corresponding receive complete register (rxpr) bit is also set to 1 simultaneously. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * when mailbox n (n = 0 to 15) has received the remote frame error-free, rfprn (n = 0 to 15) is set to 1. [setting condition] ? completion of remote frame reception in corresponding mailbox [clearing condition] ? writing 1 note: * only 1 can be written for clearing the flag. rev. 0.5, 03/03, page 280 of 438 11.3.11 interrupt register (irr) irr is an interrupt flag register. bit bit name initial value r/w description 15 irr7 0 r/(w) * overload frame [setting condition] ? when an overload frame is transmitted in error active/passive state [clearing condition] ? writing 1 14 irr6 0 r/(w) * bus off interrupt flag status flag indicating the bus off state caused by the transmit error counter. [setting condition] ? when tec 256 [clearing condition] ? writing 1 13 irr5 0 r/(w) * error passive interrupt flag status flag indicating the error passive state caused by the transmit/receive error counter. [setting condition] when tec 128 or rec 128 [clearing condition] ? writing 1 12 irr4 0 r/(w) * receive overload warning interrupt flag status flag indicating the error warning state caused by the receive error counter. [setting condition] when rec 96 [clearing condition] ? writing 1 rev. 0.5, 03/03, page 281 of 438 bit bit name initial value r/w description 11 irr3 0 r/(w) * transmit overload warning interrupt flag status flag indicating the error warning state caused by the transmit error counter. [setting condition] ? when tec 96 [clearing condition] ? writing 1 10 irr2 0 r remote frame request interrupt flag status flag indicating that a remote frame has been received in a mailbox (buffer). [setting condition] ? when remote frame reception is completed, when corresponding mbimr = 0 [clearing condition] ? clearing of all bits in rfpr (remote request register) 9 irr1 0 r receive message interrupt flag status flag indicating that a mailbox (buffer) receive message has been received normally. [setting condition] ? when data frame or remote frame reception is completed, when corresponding mbimr = 0 [clearing condition] ? clearing of all bits in rxpr (receive complete register) rev. 0.5, 03/03, page 282 of 438 bit bit name initial value r/w description 8 irr0 1 r/(w) * reset interrupt flag status flag indicating that the hcan module has been reset. this bit cannot be masked by the interrupt mask register (imr). if this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [setting condition] ? when the reset operation has finished after entering power-on reset or software standby mode [clearing condition] ? writing 1 7 to 5 ? all 0 ? reserved these bits are always read as 0. only 0 should be written to these bits. 4 irr12 0 r/(w) * bus operation interrupt flag status flag indicating detection of a dominant bit due to bus operation when the hcan module is in hcan sleep mode. [setting condition] ? bus operation (dominant bit) detection in hcan sleep mode [clearing condition] ? writing 1 3 2 ? ? 0 0 ? ? reserved these bits are always read as 0. only 0 should be written to these bits. 1 irr9 0 r unread interrupt flag status flag indicating that a receive message has been overwritten before being read. [setting condition] ? when umsr (unread message status register) is set [clearing condition] ? clearing of all bits in umsr (unread message status register) rev. 0.5, 03/03, page 283 of 438 bit bit name initial value r/w description 0 irr8 0 r/(w) * mailbox empty interrupt flag status flag indicating that the next transmit message can be stored in the mailbox. [setting condition] ? when txpr (transmit wait register) is cleared by completion of transmission or completion of transmission abort [clearing condition] ? writing 1 note: * only 1 can be written for clearing the flag. 11.3.12 mailbox interrupt mask register (mbimr) mbimr controls the enabling or disabling of individual mailbox (buffer) interrupt requests. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mailbox interrupt mask (mbimrx) when mbimrn (n = 1 to 15) is cleared to 0, the interrupt request in mailbox n is enabled. when set to 1, the interrupt request is masked. the interrupt source in a transmit mailbox is txpr clearing caused by transmission end or transmission cancellation. the interrupt source in a receive mailbox is rxpr setting on reception end. rev. 0.5, 03/03, page 284 of 438 11.3.13 interrupt mask register (imr) imr enables or disables interrupt requests by the irr interrupt flags. the reset interrupt flag cannot be masked. bit bit name initial value r/w description 15 imr7 1 r/w overload frame/bus off recovery interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr7) is enabled. when set to 1, ovr0 is masked. 14 imr6 1 r/w bus off interrupt mask when this bit is cleared to 0, ers0 (interrupt request by irr6) is enabled. when set to 1, ers0 is masked. 13 imr5 1 r/w error passive interrupt mask when this bit is cleared to 0, ers0 (interrupt request by irr5) is enabled. when set to 1, ers0 is masked. 12 imr4 1 r/w receive overload warning interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr4) is enabled. when set to 1, ovr0 is masked. 11 imr3 1 r/w transmit overload warning interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr3) is enabled. when set to 1, ovr0 is masked. 10 imr2 1 r/w remote frame request interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr2) is enabled. when set to 1, ovr0is masked. 9 imr1 1 r/w receive message interrupt mask when this bit is cleared to 0, rm1 (interrupt request by irr1) is enabled. when set to 1, rmi is masked. 8 ? 0rreserved this bit is always read as 0. only 0 should be written to this bit. 7 to 5 ? all 1 r reserved these bits are always read as 1. only 1 should be written to these bits. rev. 0.5, 03/03, page 285 of 438 bit bit name initial value r/w description 4 imr12 1 r/w bus operation interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr12) is enabled. when set to 1, ovr0 is masked. 3 2 ? ? 1 1 r r reserved these bits are always read as 1. only 1 should be written to these bits. 1 imr9 1 r/w unread interrupt mask when this bit is cleared to 0, ovr0 (interrupt request by irr9) is enabled. when set to 1, ovr0 is masked. 0 imr8 1 r/w mailbox empty interrupt mask when this bit is cleared to 0, sle0 (interrupt request by irr8) is enabled. when set to 1, sle0 is masked. 11.3.14 receive error counter (rec) rec is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the can bus. the count value is stipulated in the can protocol. 11.3.15 transmit error counter (tec) tec is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the can bus. the count value is stipulated in the can protocol. rev. 0.5, 03/03, page 286 of 438 11.3.16 unread message status register (umsr) umsr is a status register that indicates, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. when overwritten by a new message, data in the unread receive message is lost. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * [setting condition] when a new message is received before rxpr is cleared [clearing condition] writing 1 note: * only 1 can be written for clearing the flag. rev. 0.5, 03/03, page 287 of 438 11.3.17 local acceptance filter masks (lafml, lafmh) lafml and lafmh set the identifier bits of the message to be stored in mailbox 0 as don't care. for details, refer to section 11.4.4, message reception. the relationship between the identifier bits and mask bits are shown in the following. lafml bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w when this bit is set to 1, id-7 of the receive message identifier is not compared. when this bit is set to 1, id-6 of the receive message identifier is not compared. when this bit is set to 1, id-5 of the receive message identifier is not compared. when this bit is set to 1, id-4 of the receive message identifier is not compared. when this bit is set to 1, id-3 of the receive message identifier is not compared. when this bit is set to 1, id-2 of the receive message identifier is not compared. when this bit is set to 1, id-1 of the receive message identifier is not compared. when this bit is set to 1, id-0 of the receive message identifier is not compared. when this bit is set to 1, id-15 of the receive message identifier is not compared. when this bit is set to 1, id-14 of the receive message identifier is not compared. when this bit is set to 1, id-13 of the receive message identifier is not compared. when this bit is set to 1, id-12 of the receive message identifier is not compared. when this bit is set to 1, id-11 of the receive message identifier is not compared. when this bit is set to 1, id-10 of the receive message identifier is not compared. when this bit is set to 1, id-9 of the receive message identifier is not compared. when this bit is set to 1, id-8 of the receive message identifier is not compared. rev. 0.5, 03/03, page 288 of 438 lafmh bit bit name initial value r/w description 15 14 13 lafmh7 lafmh6 lafmh5 0 0 0 r/w r/w r/w when this bit is set to 1, id-20 of the receive message identifier is not compared. when this bit is set to 1, id-19 of the receive message identifier is not compared. when this bit is set to 1, id-18 of the receive message identifier is not compared. 12 to 10 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits. 9 8 7 6 5 4 3 2 1 0 lafmh1 lafmh0 lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w when this bit is set to 1, id-17 of the receive message identifier is not compared. when this bit is set to 1, id-16 of the receive message identifier is not compared. when this bit is set to 1, id-28 of the receive message identifier is not compared. when this bit is set to 1, id-27 of the receive message identifier is not compared. when this bit is set to 1, id-26 of the receive message identifier is not compared. when this bit is set to 1, id-25 of the receive message identifier is not compared. when this bit is set to 1, id-24 of the receive message identifier is not compared. when this bit is set to 1, id-23 of the receive message identifier is not compared. when this bit is set to 1, id-22 of the receive message identifier is not compared. when this bit is set to 1, id-21 of the receive message identifier is not compared. rev. 0.5, 03/03, page 289 of 438 11.3.18 message control (mc0 to mc15) the message control register sets consist of eight 8-bit registers for one mailbox. the hcan has 16 sets of these registers. because message control registers are in ram, their initial values after power-on are undefined. be sure to initialize them by writing 0 or 1. figure 11.2 shows the register names for each mailbox. mc0[1] mc1[1] mc2[1] mc3[1] mc15[1] mc0[2] mc1[2] mc2[2] mc3[2] mc15[2] mc0[3] mc1[3] mc2[3] mc3[3] mc15[3] mc0[4] mc1[4] mc2[4] mc3[4] mc15[4] mc0[5] mc1[5] mc2[5] mc3[5] mc15[5] mc0[6] mc1[6] mc2[6] mc3[6] mc15[6] mc0[7] mc1[7] mc2[7] mc3[7] mc15[7] mc0[8] mc1[8] mc2[8] mc3[8] mc15[8] mail box 0 mail box 1 mail box 2 mail box 3 mail box 15 figure 11.2 message control register configuration the setting of message control registers are shown in the following. figures 11.3 and 11.4 show the correspondence between the identifiers and register bit names. sof id-28 id-27 id-18 rtr ide r0 identifier figure 11.3 standard format sof id-28 id-27 id-18 srr ide id-17 id-16 id-0 rtr r1 standard identifier extended identifier figure 11.4 extended format rev. 0.5, 03/03, page 290 of 438 register name bit bit name r/w description 7 to 4 ? r/w the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). mcx[1] 3 to 0 dlc3 to dlc0 r/w data length code set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 byte 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes : : 1111: 8 bytes mcx[2] mcx[3] mcx[4] 7 to 0 7 to 0 7 to 0 ? ? ? r/w r/w r/w the initial value of these bits is undefined; they must be initialized (by writing 0 or 1). 7 to 5 id-20 to id-18 r/w sets id-20 to id-18 in the identifier. 4 rtr r/w remote transmission request used to distinguish between data frames and remote frames. 0: data frame 1: remote frame 3 ide r/w identifier extension used to distinguish between the standard format and extended format of data frames and remote frames. 0: standard format 1: extended format 2 ? r/w the initial value of this bit is undefined. it must be initialized by writing 0 or 1. mcx[5] 1 to 0 id-17 to id-16 r/w sets id-17 and id-16 in the identifier. mcx[6] 7 to 0 id-28 to id-21 r/w sets id-28 to id-21 in the identifier. mcx[7] 7 to 0 id-7 to id-0 r/w sets id-7 to id-0 in the identifier. mcx[8] 7 to 0 id-15 to id-8 r/w sets id-15 to id-8 in the identifier. note: x: mailbox number rev. 0.5, 03/03, page 291 of 438 11.3.19 message data (md0 to md15) the message data register sets consist of eight 8-bit registers for one mailbox. the hcan has 16 sets of these registers. because message data registers are in ram, their initial values after power- on are undefined. be sure to initialize them by writing 0 or 1. figure 11.5 shows the register names for each mailbox. md0[1] md1[1] md2[1] md3[1] md15[1] md0[2] md1[2] md2[2] md3[2] md15[2] md0[3] md1[3] md2[3] md3[3] md15[3] md0[4] md1[4] md2[4] md3[4] md15[4] md0[5] md1[5] md2[5] md3[5] md15[5] md0[6] md1[6] md2[6] md3[6] md15[6] md0[7] md1[7] md2[7] md3[7] md15[7] md0[8] md1[8] md2[8] md3[8] md15[8] mail box 0 mail box 1 mail box 2 mail box 3 mail box 15 figure 11.5 message data configuration 11.3.20 hcan monitor register (hcanmon) hcanmon enables/disables an interrupt by the hcan reception, controls transmit stop by the htxd pin, and reflects the states of the hcan pins. rev. 0.5, 03/03, page 292 of 438 bit bit name initial value r/w description 7 rxdie 0 r/w hrxd interrupt enable selects whether the irq2 interrupt is input from the pf0 pin or hrxd pin. 0: irq2 interrupt generated by input of the pf0 pin 1: irq2 interrupt generated by input of the hrxd pin 6 txstp 0 r/w htxd transmit stop bit controls the transmit stop by the htxd pin. 0: the htxd pin enables transmission. 1: the htxd pin is fixed to output 1 and transmission is stopped. 5 to 2 ? undefined ? reserved the read value is undefined. these bits cannot be modified. 1 txd undefined r transmission pin the state of the htxd pin is read. this bit cannot be modified. 0 rxd undefined r reception pin the state of the hrxd pin is read. this bit cannot be modified. rev. 0.5, 03/03, page 293 of 438 11.4 operation 11.4.1 hardware and software resets the hcan can be reset by a hardware reset or software reset. ? hardware reset at power-on reset, or in hardware or software standby mode, the hcan is initialized by automatically setting the mcr reset request bit (mcr0) in mcr and the reset state bit (gsr3) in gsr. at the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset. ? software reset the hcan can be reset by setting the mcr reset request bit (mcr0) in mcr via software. in a software reset, the error counters (tec and rec) are initialized, however other registers are not. if the mcr0 bit is set while the can controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. the reset status bit (gsr3) in gsr is set on completion of initialization. 11.4.2 initialization after hardware reset after a hardware reset, the following initialization processing should be carried out: 1. clearing of irr0 bit in the interrupt register (irr) 2. bit rate setting 3. mailbox transmit/receive settings 4. mailbox (ram) initialization 5. message transmission method setting these initial settings must be made while the hcan is in bit configuration mode. configuration mode is a state in which the gsr3 bit in gsr is set to 1 by a reset. configuration mode is exited by clearing the mcr0 bit in mcr to 0; when the mcr0 bit is cleared to 0, the hcan automatically clears the gsr3 bit in gsr. there is a delay between clearing the mcr0 bit and clearing the gsr3 bit because the hcan needs time to be internally reset, there is a delay between clearing of the mcr0 bit and gsr3 bit. after the hcan exits configuration mode, the power-up sequence begins, and communication with the can bus is possible as soon as 11 consecutive recessive bits have been detected. irr0 clearing: the reset interrupt flag (irr0) is always set after a power-on reset or recovery from software standby mode. as an hcan interrupt is initiated immediately when interrupts are enabled, irr0 should be cleared. rev. 0.5, 03/03, page 294 of 438 hardware reset mcr0 = 1 (automatic) irr0 = 1 (automatic) gsr3 = 1 (automatic) mcr0 = 0 gsr3 = 0? yes no gsr3 = 0 & 11 recessive bits received? can bus communication enabled yes no bit configuration mode period in which bcr, mbcr, etc., are initialized : settings by user : processing by hardware initialization of hcan module clear irr0 bcr setting mbcr setting mailbox initialization message transmission method initialization imr setting (interrupt mask setting) mbimr setting (interrupt mask setting) mc[x] setting (receive identifier setting) lafm setting (receive identifier mask setting) figure 11.6 hardware reset flowchart rev. 0.5, 03/03, page 295 of 438 mcr0 = 1 gsr3 = 1 (automatic) initialization of rec and tec only mcr0 = 0 gsr3 = 0? can bus communication enabled bus idle? yes correction yes correction : settings by user : processing by hardware no no no no no bcr setting mbcr setting mailbox (ram) initialization message transmission method initialization ok? imr setting mbimr setting mc[x] setting lafm setting ok? gsr3 = 0 & 11 recessive bits received? yes yes yes figure 11.7 software reset flowchart rev. 0.5, 03/03, page 296 of 438 bit rate and bit timing settings: the bit rate and bit timing settings are made in the bit configuration register (bcr). settings should be made such that all can controllers connected to the can bus have the same baud rate and bit width. the 1-bit time consists of the total of the settable time quantum (tq). sync_seg prseg phseg1 phseg2 time segment 2 (tseg2) time segment 1 (tseg1) 1-bit time (8 ? 25 time quanta) 2 ? 16 time quanta 1 time quantum figure 11.8 detailed description of one bit sync_seg is a segment for establishing the synchronization of nodes on the can bus. normal bit edge transitions occur in this segment. prseg is a segment for compensating for the physical delay between networks. phseg1 is a buffer segment for correcting phase drift (positive). this segment is extended when synchronization (resynchronization) is established. phseg2 is a buffer segment for correcting phase drift (negative). this segment is shortened when synchronization (resynchronization) is established. limits on the settable value (tseg1, tseg2, brp, sample point, and sjw) are shown in table 11.2. table 11.2 limits for settable value name abbreviation min. value max. value time segment 1 tseg1 b?0011 * 2 b?1111 time segment 2 tseg2 b?001 * 3 b?111 baud rate prescaler brp b?000000 b?111111 bit sample point bsp b?0 b?1 re-synchronization jump width sjw * 1 b?00 b?11 notes: 1. sjw is stipulated in the can specifications: 3 sjw 0 2. the minimum value of tseg2 is stipulated in the can specifications: tseg2 sjw 3. the minimum value of tseg1 is stipulated in the can specifications: tseg1 > tseg2 rev. 0.5, 03/03, page 297 of 438 time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (brp) as follows. f clk is the system clock frequency. tq = 2 (bpr setting + 1)/f clk the following formula is used to calculate the 1-bit time and bit rate. 1-bit time = tq (3 + tseg1 + tseg2) bit rate = 1/bit time = f clk /{2 (bpr setting + 1) (3 + tseg1 + tseg2)} note: f clk = (system clock) a bcr value is used for brp, tseg1, and tseg2. example: with a system clock of 24 mhz, a brp setting of b'000000, a tseg1 setting of b'0101, and a tseg2 setting of b 100: bit rate = 24/{2 (0 + 1) (3 + 5 + 4)} = 1 mbps table 11.3 setting range for tseg1 and tseg2 in bcr tseg2 (bcr[14:12]) 001 010 011 100 101 110 111 tseg1 0011 no yes no no no no no (bcr[11:8]) 0100 yes * yes yes no no no no 0101 yes * yes yes yes no no no 0110 yes * yes yes yes yes no no 0111 yes * yes yes yes yes yes no 1000 yes * yes yes yes yes yes yes 1001 yes * yes yes yes yes yes yes 1010 yes * yes yes yes yes yes yes 1011 yes * yes yes yes yes yes yes 1100 yes * yes yes yes yes yes yes 1101 yes * yes yes yes yes yes yes 1110 yes * yes yes yes yes yes yes 1111 yes * yes yes yes yes yes yes note: the time quantum value for tseg1 and tseg2 is the tseg value + 1. * only a value other than brp[13:8] = b?000000 can be set. mailbox transmit/receive settings: the hcan has 16 mailboxes. mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. the initial status of mailboxes 1 to 15 is for transmission. mailbox transmit/receive settings are not initialized by a software reset. rev. 0.5, 03/03, page 298 of 438 mailbox transmit/receive settings: the hcan has 16 mailboxes. mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. the initial status of mailboxes 1 to 15 is for transmission. mailbox transmit/receive settings are not initialized by a software reset. clearing a bit to 0 in the mailbox configuration register (mbcr) designates the corresponding mailbox for transmission use, whereas a setting of 1 in m bcr designates the corres ponding mailbox for reception use. when setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order. mailbox (message control/data) initial settings: message control/data are held in ram, and so their initial values are undefined after power is supplied. initial values must therefore be set in all the mailboxes (by writing 0s or 1s). setting the message transmission method: the following two kinds of message transmission methods are available. ? transmission order determined by message identifier priority ? transmission order determined by mailbox number priority either of the message transmission methods can be selected with the message transmission method bit (mcr2) in the master control register (mcr): when messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (txpr = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. can bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. when the txpr bit is set, the highest-priority message is found and stored in the transmit buffer. when messages are set to be transmitted according to the mailbox number proiority, if several messages are designated as waiting for transmission (txpr = 1), messages are stored in the transmit buffer in low-to-high mailbox order. can bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. rev. 0.5, 03/03, page 299 of 438 11.4.3 message transmission messages are transmitted using mailboxes 1 to 15. the transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 11.9. initialization (after hardware reset only) clear irr0 bcr setting mbcr setting mailbox initialization message transmission method setting yes no yes yes : settings by user : processing by hardware no no interrupt settings transmit data setting arbitration field setting control field setting data field setting message transmission gsr2 = 0 (during transmission only) txack = 1 irr8 = 1 clear txack clear irr8 message transmission wait txpr setting bus idle? transmission completed? imr8 = 1? interrupt to cpu end of transmission figure 11.9 transmission flowchart rev. 0.5, 03/03, page 300 of 438 cpu interrupt source settings: the cpu interrupt source is set by the interrupt mask register (imr) and mailbox interrupt mask register (mbimr). transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (mbimr). arbitration field setting: the arbitration field is set by message control registers mcx[5]? mcx[8] in a transmit mailbox. for a standard format, an 11-bit identifier (id-28 to id-18) and the rtr bit are set, and the ide bit is cleared to 0. for an extended format, a 29-bit identifier (id-28 to id-0) and the rtr bit are set, and the ide bit is set to 1. control field setting: in the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. the register to be set is the message control register mcx[1] in a transmit mailbox. data field setting: in the data field, the data to be transmitted is set within the range zero to eight. the registers to be set are the message data registers mdx[1]?mdx[8]. the byte length of the data to be transmitted is determined by the data length code in the control field. even if data exceeding the value set in the control field is set in the data field, up to the byte length set in the control field will actually be transmitted. message transmission: if the corresponding mailbox transmit wait bit (txpr1?txpr15) in the transmit wait register (txpr) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. if the message is transmitted error-free, the corresponding acknowledge bit (txack1?txack15) in the transmit acknowledge register (txack) is set to 1, and the corresponding transmit wait bit (txpr1?txpr15) in the transmit wait register (txpr) is automatically cleared to 0. also, if the corresponding bit (mbimr1- mbimr15) in the mailbox interrupt mask register (mbimr) and the mailbox empty interrupt bit (irr8) in the interrupt mask register (imr) are both simultaneously set to enable interrupts, interrupts may be sent to the cpu. if transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: ? can bus arbitration failure (failure to acquire the bus) ? error during transmission (bit error, stuff error, crc error, frame error, or ack error) message transmission cancellation: transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. a transmit wait message is canceled by setting the bit for the corresponding mailbox (txcr1?txcr15) to 1 in the transmit cancel register (txcr). clearing the transmit wait register (txpr) does not cancel transmission. when cancellation is executed, the transmit wait register (txpr) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (aback). an interrupt to the cpu can be requested, and if the mailbox empty interrupt (irr8) is enabled for the bits (mbimr1-mbimr15) corresponding rev. 0.5, 03/03, page 301 of 438 to the mailbox interrupt mask register (mbimr) and interrupt mask register (imr), interrupts may be sent to the cpu. however, a transmit wait message cannot be canceled at the following times: ? during internal arbitration or can bus arbitration ? during data frame or remote frame transmission figure 11.10 shows a flowchart for transmit message cancellation. message transmit wait txpr setting yes no yes no : settings by user : processing by hardware set txcr bit corresponding to message to be canceled message not sent clear txcr, txpr aback = 1 irr8 = 1 clear txack clear aback clear irr8 completion of message transmission txack = 1 clear txcr, txpr irr8 = 1 cancellation possible? imr8 = 1? end of transmission/transmission cancellation interrupt to cpu figure 11.10 transmit message cancellation flowchart rev. 0.5, 03/03, page 302 of 438 11.4.4 message reception the reception procedure after initial settings is described below. a reception flowchart is shown in figure 11.11. rxpr irr1 = 1 no imr2 = 1? interrupt to cpu yes no yes yes yes no : settings by user : processing by hardware no yes initialization clear irr0 bcr setting mbcr setting mailbox (ram) initialization receive data setting arbitration field setting local acceptance filter settings interrupt settings message reception (match of identifier in mailbox?) same rxpr = 1? imr1 = 1? data frame? interrupt to cpu clear irr1 end of reception clear irr2, irr1 unread message no rxpr, rfpr = 1 irr2 = 1, irr1 = 1 message control read message data read message control read message data read transmission of data frame corresponding to remote frame figure 11.11 reception flowchart rev. 0.5, 03/03, page 303 of 438 cpu interrupt source settings: cpu interrupt source settings are made in the interrupt mask register (imr) and mailbox interrupt register (mbimr). the message to be received is also specified. data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the mbimr. arbitration field setting: to receive a message, the message identifier must be set in advance in the message control registers (mcx[1]?mcx[8]) for the receiving mailbox. when a message is received, all the bits in the receive message identifier are compared with those in each message control register identifier, and if a 100% match is found, the message is stored in the matching mailbox. mailbox 0 has a local acceptance filter mask (lafm) that allows don't care settings to be made. the lafm setting can be made only for mailbox 0. by making the don't care setting for all the bits in the receive message identifier, messages of multiple identifiers can be received. examples: ? when the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: identifier 1: 010_1010_1010 ? when the identifier of mailbox 0 is 010_1010_1010 (standard format) and the lafm setting is 000_0000_0011 (0: care, 1: don't care), a total of four kinds of message identifiers can be received by mailbox 0: identifier 1: 010_1010_1000 identifier 2: 010_1010_1001 identifier 3: 010_1010_1010 identifier 4: 010_1010_1011 message reception: when a message is received, a crc check is performed automatically. if the result of the crc check is normal, ack is transmitted in the ack field irrespective of whether the message can be received or not. ? data frame reception if the received message is confirmed to be error-free by the crc check, the identifier in the mailbox (and also lafm in the case of mailbox 0 only) and the identifier of the receive message, are compared. if a complete match is found, the message is stored in the mailbox. the message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. if a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (rxpr0?rxpr15) is set in the receive complete register (rxpr). however, when a mailbox 0 lafm comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. it is therefore possible for a message matching mailbox 0 to be received by another mailbox. note that the same message cannot be stored in more than one of mailboxes 1 to 15. on receiving a message, a cpu interrupt request may be generated rev. 0.5, 03/03, page 304 of 438 depending on the mailbox interrupt mask register (mbimr) and interrupt mask register (imr) settings. ? remote frame reception two kinds of messages?data frames and remote frames?can be stored in mailboxes. a remote frame differs from a data frame in that the remote transmission request bit (rtr) in the message control register and the data field is 0 bytes long. the data length to be returned in a data frame must be stored in the data length code (dlc) in the control field. when a remote frame (rtr = recessive) is received, the corresponding bit is set in the remote request wait register (rfpr). if the corresponding bit (mbimr0?mbimr15) in the mailbox interrupt mask register (mbimr) and the remote frame request interrupt mask (irr2) in the interrupt mask register (imr) are set to the interrupt enable value at this time, an interrupt can be sent to the cpu. unread message overwrite: if the receive message identifier matches the mailbox identifier, the receive message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. if a message overwrite occurs, the corresponding bit (umsr0?umsr15) is set in the unread message register (umsr). in overwriting an unread message, when a new message is received before the corresponding bit in the receive complete register (rxpr) has been cleared, the unread message register (umsr) is set. if the unread interrupt flag (irr9) in the interrupt mask register (imr) is set to the interrupt enable value at this time, an interrupt can be sent to the cpu. figure 11.12 shows a flowchart for unread message overwriting. no : settings by user unread message overwrite interrupt to cpu end imr9 = 1? umsr = 1 irr9 = 1 clear irr9 message control/message data read : processing by hardware yes figure 11.12 unread message overwrite flowchart rev. 0.5, 03/03, page 305 of 438 11.4.5 hcan sleep mode the hcan is provided with an hcan sleep mode that places the hcan module in the sleep state in order to reduce current consumption. figure 11.13 shows a flowchart of the hcan sleep mode. irr12 = 1 yes mcr5 = 0 yes yes mcr5 = 0 clear sleep mode? yes no no no yes (manual) no (automatic) mcr5 = 1 bus idle? initialize tec and rec bus operation? : settings by user : processing by hardware no no imr12 = 1? sleep mode clearing method mcr7 = 0? 11 recessive bits? can bus communication possible cpu interrupt figure 11.13 hcan sleep mode flowchart rev. 0.5, 03/03, page 306 of 438 hcan sleep mode is entered by setting the hcan sleep mode bit (mcr5) to 1 in the master control register (mcr). if the can bus is operating, the transition to hcan sleep mode is delayed until the bus becomes idle. either of the following methods of clearing hcan sleep mode can be selected: ? clearing by software ? clearing by can bus operation eleven recessive bits must be received after hcan sleep mode is cleared before can bus communication is re-enabled. clearing by software: hcan sleep mode is cleared by writing a 0 to mcr5 from the cpu. clearing by can bus operation: the cancellation method is selected by the mcr7 bit setting in mcr. clearing by can bus operation occurs automatically when the can bus performs an operation and this change is detected. in this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. when a change is detected on the can bus in hcan sleep mode, the bus operation interrupt flag (irr12) is set in the interrupt register (irr). if the bus interrupt mask (imr12) in the interrupt mask register (imr) is set to the interrupt enable value at this time, an interrupt can be sent to the cpu. 11.4.6 hcan halt mode the hcan halt mode is provided to enable mailbox settings to be changed without performing an hcan hardware or software reset. figure 11.14 shows a flowchart of the hcan halt mode. mcr1 = 1 yes : settings by user : processing by hardware no bus idle? mbcr setting mcr1 = 0 can bus communication possible figure 11.14 hcan halt mode flowchart rev. 0.5, 03/03, page 307 of 438 hcan halt mode is entered by setting the halt request bit (mcr1) to 1 in the master control register (mcr). if the can bus is operating, the transition to hcan halt mode is delayed until the bus becomes idle. hcan halt mode is cleared by clearing mcr1 to 0. 11.5 interrupt sources table 11.4 lists the hcan interrupt sources. with the exception of the reset processing vector (irr0), these sources can be masked. masking is implemented using the mailbox interrupt mask register (mbimr), interrupt mask register (imr), and irq enable register (ier). for details on the interrupt vector of each interrupt source, refer to section 5, interrupt controller. table 11.4 hcan interrupt sources name description interrupt flag error passive interrupt (tec 128 or rec 128) irr5 bus off interrupt (tec 256) irr6 reset process interrupt by power-on reset irr0 remote frame reception irr2 error warning interrupt (tec 96) irr3 error warning interrupt (rec 96) irr4 overload frame transmission irr7 unread message overwrite irr9 ers0/ovr0 detection of can bus operation in hcan sleep mode irr12 rm0 mailbox 0 message reception irr1 rm1 mailbox 1-15 message reception irr1 sle0 message transmission/cancellation irr8 irq2 generation of irq2 interrupt from hrxd input pin by setting rxdie bit in hcanmon to 1 irq2f rev. 0.5, 03/03, page 308 of 438 11.6 can bus interface a bus transceiver ic is necessary to connect this chip to a can bus. a philips pca82c250 transceiver ic is recommended. any other product must be compatible with the pca82c250. figure 11.15 shows a sample connection diagram. rs rxd txd vref vcc canh canl gnd hrxd nc note: nc: no connection htxd this lsi can bus 124 124 vcc pca82c250 figure 11.15 high-speed interface using pca82c250 11.7 usage notes 11.7.1 module stop mode setting hcan operation can be disabled or enabled using the module stop control register. the initial setting is for hcan operation to be halted. register access is enabled by clearing module stop mode. for details, refer to section 16, power-down modes. 11.7.2 reset the hcan is reset by a power-on reset, in hardware standby mode, and in software standby mode. all the registers are initialized in a reset, however mailboxes (message control (mcx[x])/message data (mdx[x])) are not. after power-on, mailboxes (message control (mcx[x])/message data (mdx[x])) are initialized, and their values are undefined. therefore, mailbox initialization must always be carried out after a power-on reset, a transition to hardware standby mode, or software standby mode. the reset interrupt flag (irr0) is always set after a power-on reset or recovery from software standby mode. as this bit cannot be masked in the interrupt mask register (imr), if hcan interrupt enabling is set in the interrupt controller without clearing the flag, an hcan interrupt will be initiated immediately. irr0 should therefore be cleared during initialization. rev. 0.5, 03/03, page 309 of 438 11.7.3 hcan sleep mode the bus operation interrupt flag (irr12) in the interrupt register (irr) is set by can bus operation in hcan sleep mode. therefore, this flag is not used by the hcan to indicate sleep mode release. note that the reset status bit (gsr3) in the general status register (gsr) is set in sleep mode. 11.7.4 interrupts when the mailbox interrupt mask register (mbimr) is set, the interrupt register (irr8, 2, 1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. 11.7.5 error counters in the case of error active and error passive, rec and tec normally count up and down. in the bus-off state, 11-bit recessive sequences are counted (rec + 1) using rec. if rec reaches 96 during the count, irr4 and gsr1 are set. 11.7.6 register access byte or word access can be used on all hcan registers. longword access cannot be used. 11.7.7 hcan medium-speed mode in medium-speed mode, neither read nor write is possible for the hcan registers. 11.7.8 register hold in standby modes all hcan registers are initialized in hardware standby mode and software standby mode. 11.7.9 use on bit manipulation instructions since the hcan status flag is cleared by writing 1, do not use the bit manipulation instructions to clear the flag. to clear the flag, use the mov instructions and write 1 only to the bit to be cleared. rev. 0.5, 03/03, page 310 of 438 11.7.10 hcan txcr operation 1. when the transmit wait cancel register (txcr) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to txcr and the transmit wait register (txpr) may not be cleared even if transmission is canceled. this occurs when the following conditions are all satisfied. ? the hrxd pin is stacked to 1 because of a can bus error, etc. ? there is at least one mailbox waiting for transmission or being transmitted. ? the message transmission in a mailbox being transmitted is canceled by txcr. if this occurs, transmission is canceled. however, since txpr and txcr states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the hrxd pin is canceled and the can bus recovers the normal state. if there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. to avoid this, one of the following countermeasures must be executed. ? transmission must not be canceled by txcr. when transmission is normally completed after the can bus has recovered, txpr is cleared and the hcan recovers the normal state. ? to cancel transmission, the corresponding bit to txcr must be written to 1 continuously until the bit becomes 0. txpr and txcr are cleared and the hcan recovers the normal state. 2. when the bus-off state is entered while txpr is set and the transmit wait state is entered, the internal state machine does not operate even if txcr is set during the bus-off state. therefore transmission cannot be canceled. the message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. to clear a message after the bus-off state is recovered, the following countermeasure must be executed. ? a transmit wait message must be cleared by resetting the hcan during the bus-off period. to reset the hcan, the module stop bit (mstpc3 in mstpcrc) must be set or cleared. in this case, the hcan is entirely reset. therefore the initial settings must be made again. adcms00b_000020020200 rev. 0.5, 03/03, page 311 of 438 section 12 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to 16 analog input channels to be selected. the block diagram of the a/d converter is shown in figure 12.1. 12.1 features ? 10-bit resolution ? 16 input channels ? conversion time: 11.08 s per channel (at 24 mhz operation) ? two operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a 16-bit data register for each channel ? sample and hold function ? three methods conversion start ? software ? 16-bit timer pulse unit (tpu) conversion start trigger ? external trigger signal ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated ? module stop mode can be set rev. 0.5, 03/03, page 312 of 438 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface successive approximations register multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a an0 an1 an2 an3 an4 an5 an6 an7 legend adcr : a/d control register adcsr : a/d control/status register addra : a/d data register a addrb : a/d data register b addrc : a/d data register c addrd : a/d data register d conversion start trigger from tpu an8 an9 an10 an11 an12 an13 an14 an15 /2 /4 /8 /16 av cc av ss figure 12.1 block diagram of a/d converter rev. 0.5, 03/03, page 313 of 438 12.2 input/output pins table 12.1 summarizes the input pins used by the a/d converter. the 16 analog input pins are divided into four channel sets and four groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1, analog input pins 8 to 11 (an8 to an11) comprising group 2, and analog input pins 12 to 15 (an12 to an15) comprising group 3. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. table 12.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply and reference voltage analog ground pin av ss input analog block ground and reference voltage analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input pins analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input pins analog input pin 8 an8 input analog input pin 9 an9 input analog input pin 10 an10 input analog input pin 11 an11 input group 2 analog input pins analog input pin 12 an12 input analog input pin 13 an13 input analog input pin 14 an14 input analog input pin 15 an15 input group 3 analog input pins a/d external trigger input pin adtrg input external trigger input pin for starting a/d conversion rev. 0.5, 03/03, page 314 of 438 12.3 register descriptions the a/d converter has the following registers. the mstpa1 bit in the module stop control register a (mstpcra) specifies the modes of this module as module stop mode. for details on mstpcra, refer to section 16.1.3, module stop control registers a to c (mstpcra to mstpcrc). ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) ? a/d control register (adcr) 12.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which store a conversion result for each channel, are shown in table 12.2. the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converter is 8 bits wide. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register contents are transferred from the addr when the upper byte data is read. when reading the addr, read the upper byte before the lower byte, or read in word unit. when only the lower byte is read, the contents are not guaranteed. table 12.2 analog input channels and corresponding addr registers analog input channel ch3 = 0 ch3 = 1 group 0 (ch2 = 0) group 1 (ch2 = 1) group 2 (ch2 = 0) group 3 (ch2 = 1) a/d data register to be stored results of a/d conversion an0 an4 an8 an12 addra an1 an5 an9 an13 addrb an2 an6 an10 an14 addrc an3 an7 an11 an15 addrd rev. 0.5, 03/03, page 315 of 438 12.3.2 a/d control/status register (adcsr) adcsr controls a/d conversion operations. bit bit name initial value r/w description 7 adf 0 r/(w) a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? when a/d conversion ends ? when a/d conversion ends on all specified channels [clearing condition] ? when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt (adi) request enabled when 1 is set 5 adst 0 r/w a/d start clearing this bit to 0 stops a/d conversion, and the a/d converter enters the wait state. setting this bit to 1 starts a/d conversion. in single mode, this bits is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode rev. 0.5, 03/03, page 316 of 438 bit bit name initial value r/w description 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 0 to 3 select analog input channels. when scan = 0 when scan = 1 0000: an0 0000: an0 0001: an1 0001: an0, an1 0010: an2 0010: an0 to an2 0011: an3 0011: an0 to an3 0100: an4 0100: an4 0101: an5 0101: an4, an5 0110: an6 0110: an4 to an6 0111: an7 0111: an4 to an7 1000: an8 1000: an8 1001: an9 1001: an8, an9 1010: an10 1010: an8 to an10 1011: an11 1011: an8 to an11 1100: an12 1100: an12 1101: an13 1101: an12, an13 1110: an14 1110: an12 to an14 1111: an15 1111: an12 to an15 rev. 0.5, 03/03, page 317 of 438 12.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 6 trgs1 trgs0 0 0 r/w r/w timer trigger select 0 and 1 enables the start of a/d conversion by a trigger signal. only set bits trgs0 and trgs1 while conversion is stopped (adst = 0). 00: a/d conversion start by software is enabled 01: a/d conversion start by tpu conversion start trigger is enabled 10: setting prohibited 11: a/d conversion start by external trigger pin ( adtrg ) is enabled 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 2 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits specify the a/d conversion time. the conversion time should be changed only when adst = 0. specify a setting that gives a value within the range shown in table 18.7 in section 18, electrical characteristics. 00: conversion time = 530 states (max.) 01: conversion time = 266 states (max.) 10: conversion time = 134 states (max.) 11: conversion time = 68 states (max.) 1 0 ? ? 1 1 ? ? reserved these bits are always read as 1. rev. 0.5, 03/03, page 318 of 438 12.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit adst to 0 in adcsr. the adst bit can be set at the same time as the operating mode or analog input channel is changed. 12.4.1 single mode in single mode, a/d conversion is to be performed only once on the specified single channel. the operations are as follows. 1. a/d conversion is started when the adst bit is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the result is transferred to the corresponding a/d data register to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d converion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 12.4.2 scan mode in scan mode, a/d conversion is to be performed sequentially on the specified channels (four channels maximum). the operations are as follows. 1. when the adst bit is set to 1 by software, tpu or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch3 and ch2 = 00, an4 when ch3 and ch2 = 01, an8 when ch3 and ch2 = 10, or an12 when ch3 and ch2 = 11). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. conversion of the first channel in the group starts again. 4. steps [2] to [3] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and the a/d converter enters the wait state. rev. 0.5, 03/03, page 319 of 438 12.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 12.2 shows the a/d conversion timing. table 12.3 shows the a/d conversion time. as indicated in figure 12.2, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 12.3. in scan mode, the values given in table 12.3 apply to the first conversion time. the values given in table 12.4 apply to the second and subsequent conversions. in both cases, set bits cks1 and cks0 in adcr to give an a/d conversion time within the range shown in table 18.7 in section 18, electrical characteristics. (1) (2) t d t spl t conv address write signal input sampling timing adf legend (1) : adcsr write cycle (2) : adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 12.2 a/d conversion timing rev. 0.5, 03/03, page 320 of 438 table 12.3 a/d conversion time (single mode) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay t d 18 ? 33 10 ? 17 6 ? 9 4 ? 5 input sampling time t spl ? 127 ? ? 63 ? ? 31 ? ? 15 ? a/d conversion time t conv 515 ? 530 259 ? 266 131 ? 134 67 ? 68 note: all values represent the number of states. table 12.4 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 512 (fixed) 0 1 256 (fixed) 0 128 (fixed) 1 1 64 (fixed) rev. 0.5, 03/03, page 321 of 438 12.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs0 and trgs1 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 12.3 shows the timing. internal trigger signal adst a/d conversion figure 12.3 external trigger input timing 12.5 interrupt sources the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. setting the adie bit to 1 enables adi interrupt requests while the bit adf in adcsr is set to 1 after a/d conversion is completed. table 12.5 a/d converter interrupt source name interrupt source interrupt source flag adi a/d conversion completed adf rev. 0.5, 03/03, page 322 of 438 12.6 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 12.4). ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 12.5). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 12.5). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between zero voltage and full- scale voltage. does not include offset error, full-scale error, or quantization error (see figure 12.5). ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization error, and nonlinearity error. rev. 0.5, 03/03, page 323 of 438 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 12.4 a/d conversion accuracy definitions fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 12.5 a/d conversion accuracy definitions rev. 0.5, 03/03, page 324 of 438 12.7 usage notes 12.7.1 module stop mode setting operation of the a/d converter can be disabled or enabled using the module stop control register. the initial setting is for operation of the a/d converter to be halted. register access is enabled by clearing module stop mode. for details, refer to section 16, power-down modes. 12.7.2 permissible signal source impedance this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k ? or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. however, for a/d conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 12.6). when converting a high-speed analog signal, a low-impedance buffer should be inserted. 12.7.3 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e, acting as antennas). 20 pf 10 k c in = 15 pf sensor output impedance to 5 k this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 12.6 example of analog input circuit rev. 0.5, 03/03, page 325 of 438 12.7.4 range of analog power supply and other pin settings if the conditions below are not met, the reliability of the device may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann avcc. ? relationship between avcc, avss and vcc, vss set avss = vss as the relationship between avcc, avss and vcc, vss. if the a/d converter is not used, the avcc and avss pins must not be left open. 12.7.5 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an15), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. 12.7.6 notes on noise countermeasures a protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (an0 to an15), between avcc and avss, as shown in figure 12.7. also, the bypass capacitors connected to avcc and the filter capacitor connected to an0 to an15 must be connected to avss. if a filter capacitor is connected, the input currents at the analog input pins (an0 to an15) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding circuit constants. rev. 0.5, 03/03, page 326 of 438 avcc * 1 an0 to an15 avss r in * 2 100 0.1 f 0.01 f 10 f notes: values are reference values. 1. 2. r in : input impedance figure 12.7 example of analog input protection circuit table 12.6 analog pin specifications item min. max. unit analog input capacitance ? 20 pf permissible signal source impedance ? 5k ? 20 pf an0 to an15 note: values are reference values. 10 k to a/d converter figure 12.8 analog input pin equivalent circuit rev. 0.5, 03/03, page 327 of 438 section 13 ram this lsi has 4 kbytes of on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. the on-chip ram can be enabled or disabled by means of the rame bit in the system control register (syscr). for details on syscr, refer to section 3.2.2, system control register (syscr). rev. 0.5, 03/03, page 328 of 438 rom3120a_000020020200 rev. 0.5, 03/03, page 329 of 438 section 14 rom the features of the flash memory are summarized below. the block diagram of the flash memory is shown in figure 14.1. 14.1 features ? size: 64 kbytes ? programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 28 kbytes 1 block, 16 kbytes 1 block, 8 kbytes 2 blocks, and 1 kbyte 4 blocks. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability ? the flash memory can be reprogrammed up to 100 times. ? three programming modes ? boot mode ? user mode ? programmer mode ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection ? sets software protection against flash memory programming/erasing. rev. 0.5, 03/03, page 330 of 438 module bus bus interface/controller flash memory (64 kbytes) operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ramer flpwcr flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 ram emulation register flash memory power control register legend flmcr1: flmcr2: ebr1: ramer: flpwcr: figure 14.1 block diagram of flash memory 14.2 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, this lsi enters an operating mode as shown in figure 14.2. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. the differences between boot mode and user program mode are shown in table 14.1. figure 14.3 shows the operation flow for boot mode and figure 14.4 shows that for user program mode. rev. 0.5, 03/03, page 331 of 438 boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode = 0 fwe = 1 fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. this lsi transits to programmer mode by using the dedicated prom programmer. = 0 md2 = 0 md1 = 1, fwe = 1 = 0 = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 14.2 flash memory state transitions table 14.1 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm. rev. 0.5, 03/03, page 332 of 438 flash memory this lsi ram host programming control program sci application program (old version) new application program flash memory this lsi ram host sci application program (old version) boot program area new application program flash memory this lsi ram host sci flash memory preprogramming erase boot program new application program flash memory this lsi program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in this lsi (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program figure 14.3 boot mode rev. 0.5, 03/03, page 333 of 438 flash memory this lsi ram host programming/ erase control program sci boot program new application program flash memory this lsi ram host sci new application program flash memory this lsi ram host sci flash memory erase boot program new application program flash memory this lsi program execution state ram host sci boot program boot program fwe assessment program application program (old version) new application program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program figure 14.4 user program mode rev. 0.5, 03/03, page 334 of 438 14.3 block configuration figure 14.5 shows the block configuration of 64-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2 blocks), and 1 kbyte (4 blocks). erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. eb0 erase unit 1 kbyte eb1 erase unit 1 kbyte eb2 erase unit 1 kbyte eb3 erase unit 1 kbyte eb4 erase unit 28 kbytes eb5 erase unit 16 kbytes eb6 erase unit 8 kbytes eb7 erase unit 8 kbytes h'000000 h'000001 h'000002 h'00007f h'0003ff h'00047f h'00087f h'000c7f h'00107f h'007fff h'00807f h'00bfff h'0007ff h'000bff h'000fff h'00c07f h'00dfff h'00e07f h'00ffff h'000400 h'000401 h'000402 h'000780 h'000781 h'000782 h'000800 h'000801 h'000802 h'000b80 h'000b81 h'000b82 h'000f80 h'000f81 h'000f82 h'007f80 h'007f81 h'007f82 h'00bf80 h'00bf81 h'00bf82 h'00df80 h'00df81 h'00df82 h'00ff80 h'00ff81 h'00ff82 h'000c00 h'000c01 h'000c02 h'001000 h'001001 h'001002 h'008000 h'008001 h'008002 h'00c000 h'00c001 h'00c002 h'00e000 h'00e001 h'00e002 h'000380 h'000381 h'000382 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes figure 14.5 flash memory block configuration rev. 0.5, 03/03, page 335 of 438 14.4 input/output pins the flash memory is controlled by means of the pins shown in table 14.2. table 14.2 pin configuration pin name i/o function res input reset fwe input flash program/erase protection by hardware md2 input sets this lsi?s operating mode md1 input sets this lsi?s operating mode md0 input sets this lsi?s operating mode txd2 output serial transmit data output rxd2 input serial receive data input 14.5 register descriptions the flash memory has the following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? ram emulation register (ramer) ? flash memory power control register (flpwcr) rev. 0.5, 03/03, page 336 of 438 14.5.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 14.8, flash memory programming/erasing. bit bit name initial value r/w description 7fwe ? r reflects the input level at the fwe pin. it is cleared to 0 when a low level is input to the fwe pin, and set to 1 when a high level is input. 6 swe 0 r/w software write enable bit when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu1 0 r/w erase setup bit when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. 4 psu1 0 r/w program setup bit when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p1 bit in flmcr1. 3 ev1 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase- verify mode is cancelled. 2 pv1 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program-verify mode is cancelled. 1e1 0 r/w erase when this bit is set to 1, and while the swe1 and esu1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p1 0 r/w program when this bit is set to 1, and while the swe1 and psu1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. rev. 0.5, 03/03, page 337 of 438 14.5.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see section 14.9.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 14.5.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase area block. ebr1 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 eb7 0 r/w when this bit is set to 1, 8 kbytes of eb7 (h'00e000 to h'00ffff) will be erased. 6 eb6 0 r/w when this bit is set to 1, 8 kbytes of eb6 (h'00c000 to h'00dfff) will be erased. 5 eb5 0 r/w when this bit is set to 1, 16 kbytes of eb5 (h'008000 to h'00bfff) will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of eb4 (h'001000 to h'007fff) will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of eb3 (h'000c00 to h'000fff) will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of eb2 (h'000800 to h'000bff) will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of eb1 (h'000400 to h'0007ff) will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of eb0 (h'000000 to h'0003ff) will be erased. rev. 0.5, 03/03, page 338 of 438 14.5.4 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer settings should be made in user mode or user program mode. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5, 4 ? all 0 r/w reserved only 0 should be written to these bits. 3 rams 0 r/w ram select specifies selection or non-selection of flash memory emulation in ram. when rams = 1, the flash memory is overlapped with part of ram, and all flash memory block are program/erase-protected. 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area selection when the rams bit is set to 1, one of the following flash memory areas are selected to overlap the ram area of h?ffe000 to h?ffe3ff. the areas correspond with 1-kbyte erase blocks. 00x: h?000000 to h?0003ff (eb0) 01x: h?000400 to h?0007ff (eb1) 10x: h?000800 to h?000bff (eb2) 11x: h?000c00 to h?000fff (eb3) note: x: don?t care rev. 0.5, 03/03, page 339 of 438 14.5.5 flash memory power control register (flpwcr) flpwcr enables or disables a transition to the flash memory power-down mode when this lsi switches to subactive mode. bit bit name initial value r/w description 7 pdwnd 0 r/w when this bit is set to 1, the transition to flash memory power-down mode is disabled. 6 to 0 ? all 0 r reserved these bits are always read as 0. 14.6 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the md pin settings and fwe pin setting, as shown in table 14.3. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci_2. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 14.3 setting on-board programming modes md2 md1 md0 fwe lsi state after reset end 1111user mode 0 1 1 1 boot mode rev. 0.5, 03/03, page 340 of 438 14.6.1 boot mode table 14.4 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 14.8, flash memory programming/erasing. 2. sci_2 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci_2 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 14.5. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'ffe000 to h'ffe7ff is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci_2 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high. the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the mode (md) pins. boot mode is also cleared when a wdt overflow occurs. 8. do not change the md pin input levels in boot mode. 9. all interrupts are disabled during programming or erasing of the flash memory. rev. 0.5, 03/03, page 341 of 438 table 14.4 boot mode operation item host operation communications contents lsi operation boot mode start branches to boot program at reset-start. processing contents processing contents bit rate adjustment continuously transmits data h'00 at specified bit rate. h'00, h'00 ...... h'00 h'00 h'55 measures low-level period of receive data h'00. calculates bit rate and sets it in brr of sci_2. transmits data h'00 to host as adjustment end indication. transmits data h'aa to host when data h'55 is received. transmits data h'55 when data h'00 is received error-free. transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) receives data h'aa. transmits 1-byte of programming control program (repeated for n times) receives data h'aa. transfer of programming control program flash memory erase boot program initiation echobacks the 2-byte data received. branches to programming control program transferred to on-chip ram and starts execution. echobacks received data to host and also transfers it to ram (repeated for n times) checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) high-order byte and low-order byte h'xx h'aa echoback echoback h'ff h'aa boot program erase error table 14.5 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system clock frequency range of lsi 19,200 bps 24 mhz 9,600 bps 8 to 24 mhz 4,800 bps 4 to 24 mhz rev. 0.5, 03/03, page 342 of 438 14.6.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 14.6 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 14.8, flash memory programming/erasing. ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program fwe=high * clear fwe do not constantly apply a high level to the fwe pin. only apply a high level to the fwe pin when programming or erasing the flash memory. to prevent excessive programming or excessive erasing, while a high level is being applied to the fwe pin, activate the watchdog timer in case of handling cpu runaways. note: * figure 14.6 programming/erasing flowchart example in user program mode rev. 0.5, 03/03, page 343 of 438 14.7 flash memory emulation in ram a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. emulation can be performed in user mode or user program mode. figure 14.7 shows an example of emulation of real-time flash memory programming. 1. set ramer to overlap part of ram onto the area for which real-time programming is required. 2. emulation is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, thus releasing the ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). start of emulation program set ramer write tuning data to overlap ram execute application program tuning ok? clear ramer write to flash memory emulation block end of emulation program no ye s figure 14.7 flowchart for flash memory emulation in ram rev. 0.5, 03/03, page 344 of 438 an example in which flash memory block area eb0 is overlapped is shown in figure 14.8. 1. the ram area to be overlapped is fixed at a 1-kbyte area in the range h'ffe000 to h'ffe3ff. 2. the flash memory area to overlap is selected by ramer from a 1-kbyte area of the eb0 to eb3 blocks. 3. the overlapped ram area can be accessed from both the flash memory addresses and ram addresses. 4. when the rams bit in ramer is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). in this state, setting the p1 or e1 bit in flmcr1 to 1 does not cause a transition to program mode or erase mode. 5. a ram area cannot be erased by execution of software in accordance with the erase algorithm. 6. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram. h'000000 flash memory (eb0) flash memory (eb0) (eb1) (eb2) (eb3) h'0003ff h'000400 h'0007ff h'000800 h'000bff h'000c00 h'000fff h'ffe000 h'ffe3ff on-chip ram (1 k byte) on-chip ram (shadow of h'ffe000 to h'ffe3ff) flash memory (eb2) on-chip ram (1 k byte) (eb3) normal memory map ram overlap memory map figure 14.8 example of ram overlap operation rev. 0.5, 03/03, page 345 of 438 14.8 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 14.8.1, program/program-verify and section 14.8.2, erase/erase-verify, respectively. 14.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 14.9 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation and additional programming data computation according to figure 14.9. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p1 bit is set to 1 is the programming time. figure 14.9 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in longwords from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. rev. 0.5, 03/03, page 346 of 438 start end of programming set swe bit in flmcr1 start of programming write pulse application subroutine wait (t sswe ) s apply write pulse end sub set psu1 bit in flmcr1 wdt enable disable wdt number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 note 6: write pulse width write time (tsp) s 30 30 30 30 30 30 200 200 200 200 200 200 200 200 200 200 wait (t spsu ) s set p1 bit in flmcr1 wait (t sp ) s clear p1 bit in flmcr1 wait (t cp ) s clear psu1 bit in flmcr1 wait (t cpsu ) s n= 1 m= 0 no no no no yes yes yes wait (t spv ) s wait (t spvr ) s * 2 * 7 * 7 * 4 * 7 * 7 start of programming end of programming * 5 * 7 * 7 * 7 * 1 wait (t cpv ) s apply write pulse sub-routine-call set pv1 bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? * 4 * 3 * 7 * 7 * 7 * 1 transfer reprogram data to reprogram data area reprogram data computation * 4 transfer additional-programming data to additional-programming data area additional-programming data computation clear pv1 bit in flmcr1 clear swe bit in flmcr1 m = 1 reprogram see note 6 for pulse width m= 0 ? increment address programming failure yes clear swe bit in flmcr1 wait (t cswe ) s no yes 6 n? no yes 6 n ? wait (t cswe ) s n (n)? n n + 1 original data (d) verify data (v) reprogram data (x) comments programming completed still in erased state; no action programming incomplete; reprogram note: * use a 10 s write pulse for additional programming. write 128-byte data in ram reprogram data area consecutively to flash memory ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area apply write pulse (additional programming) sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory reprogram data computation table reprogram data (x') verify data (v) additional- programming data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional programming to be executed additional programming not to be executed additional programming not to be executed additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-programming data computation table perform programming in the erased state. do not perform additional programming on previously programmed addresses. notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program dat a area and the verify data). bits for which the reprogram data is 0 are programmed in the next reprogramming loop. therefore, even bits for which programming has bee n completed will be subjected to programming once again if the result of the subsequent verify operation is ng. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additio nal data must be provided in ram. the contents of the reprogram data area and additional data area are modified as programming proceeds. 5. a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing o f additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means reprogram data when the write pulse is applied. 7. the wait times and value of n are shown in section 18.5, flash memory characteristics. * * * * * * figure 14.9 program/program-verify flowchart rev. 0.5, 03/03, page 347 of 438 14.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 14.10 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e1 bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h?ff to an address whose lower two bits are b?00. verify data can be read in longwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 14.8.3 interrupt handling when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. rev. 0.5, 03/03, page 348 of 438 erase start set ebr1 enable wdt disable wdt read verify data increment address verify data = all 1s? last address of block? all erase block erased? set block start address as verify address h'ff dummy write to verify address swe bit 1 n 1 esu1 bit 1 e1 bit 1 wait 1 s wait 100 s e1 bit 0 ev1 bit 1 wait 10 s esu1 bit 0 wait 10 s wait 10 s wait 20 s ev1 bit 0 n n + 1 wait 4 s swe bit 0 wait 100 s ev1 bit 0 n 100? wait 4 s swe bit 0 wait 100 s erase failure end of erasing wait 2 s no no ye s ye s no no ye s ye s figure 14.10 erase/erase-verify flowchart rev. 0.5, 03/03, page 349 of 438 14.9 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 14.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 14.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p1 or e1 bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h?00, erase protection is set for all blocks. 14.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling (excluding a reset) during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re- entered by re-setting the p1 or e1 bit. however, pv1 and ev1 bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset. rev. 0.5, 03/03, page 350 of 438 14.10 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. use a prom programmer that supports the hitachi 64-kbyte flash memory on-chip mcu device type (fztat64v5a). 14.11 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to. ? power-down mode part of the power supply circuitry is halted, and the flash memory can be read when the lsi is operating on the subclock. ? standby mode all flash memory circuits are halted. table 14.6 shows the correspondence between the operating modes of this lsi and the flash memory. when the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 2 ms, even when the external clock is being used. table 14.6 flash memory operating states lsi operating state flash memory operating state high-speed mode medium-speed mode sleep mode normal operating mode subactive mode subsleep mode when pdwnd = 0: power-down mode (read-only) when pdwnd = 1: normal operating mode (read-only) watch mode software standby mode hardware standby mode standby mode cpg0100a_000020020200 rev. 0.5, 03/03, page 351 of 438 section 15 clock pulse generator this lsi has an on-chip clock pulse generator that generates the system clock ( ), the bus master clock, internal clock, and subclock. the clock pulse generator consists of an oscillator, pll circuit, subclock divider, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. a block diagram of the clock pulse generator is shown in figure 15.1. extal xtal sck2 to sck0 sckcr stc1, stc0 lpwrcr legend lpwrcr : low-power control register sckcr : system clock control register clock oscillator pll circuit ( 1, 2, 4) clock selection circuit system clock to pin internal clock to peripheral modules bus master clock to cpu medium- speed clock divider bus master clock selection circuit /2 to /32 sub subclock divider (division by 128) subclock to wdt1 figure 15.1 block diagram of clock pulse generator the frequency can be changed by means of the pll circuit. frequency changes are performed by software by settings in the low-power control register (lpwrcr) and system clock control register (sckcr). rev. 0.5, 03/03, page 352 of 438 15.1 register descriptions the on-chip clock pulse generator has the following registers. ? system clock control register (sckcr) ? low-power control register (lpwrcr) 15.1.1 system clock control register (sckcr) sckcr performs clock output control, selection of operation when the pll circuit frequency multiplication factor is changed, and medium-speed mode control. bit bit name initial value r/w description 7 pstop 0 r/w clock output disable controls output. high-speed mode, medium-speed mode, subactive mode, sleep mode, subsleep mode 0: output 1: fixed high software standby mode, watch mode, direct transition 0: fixed high 1: fixed high hardware standby mode 0: high impedance 1: high impedance 6 to 4 ? all 0 ? reserved these bits are always read as 0. 3 stcs 0 r/w frequency multiplication factor switching mode select selects the operation when the pll circuit frequency multiplication factor is changed. 0: specified multiplication factor is valid after transition to software standby mode 1: specified multiplication factor is valid immediately after stc1 bit and stc0 bit are rewritten rev. 0.5, 03/03, page 353 of 438 bit bit name initial value r/w description 2 1 0 sck2 sck1 sck0 0 0 0 r/w r/w r/w system clock select 0 to 2 these bits select the bus master clock. 000: high-speed mode 001: medium-speed clock is /2 010: medium-speed clock is /4 011: medium-speed clock is /8 100: medium-speed clock is /16 101: medium-speed clock is /32 11x: setting prohibited legend x: don?t care 15.1.2 low-power control register (lpwrcr) lpwrcr performs power-down mode control, subclock generation control, oscillation circuit feedback resistance control, and frequency multiplication factor setting. bit bit name initial value r/w description 7 6 dton lson 0 0 r/w r/w see section 16.1.2, low-power control register (lpwrcr). 5 ? 0r/wreserved only write 0 to this bit. 4 substp 0 r/w subclock generation control 0: enables subclock generation 1: disables subclock generation 3 rfcut 0 r/w oscillation circuit feedback resistance control 0: when the main clock is oscillating, sets the feedback resistance on. when the main clock is stopped, sets the feedback resistance off. 1: sets the feedback resistance off. change is valid when software standby mode is entered or after software standby mode is recovered. note: with a crystal resonator, the resonator will not operate if this bit is set to 1. 2 ? 0r/wreserved only write 0 to this bit. rev. 0.5, 03/03, page 354 of 438 bit bit name initial value r/w description 1 0 stc1 stc0 0 0 r/w r/w frequency multiplication factor the stc bits specify the frequency multiplication factor of the pll circuit. 00: 1 01: 2 10: 4 11: setting prohibited 15.2 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. in either case, the input clock should not exceed 24 mhz. 15.2.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 15.2. select the damping resistance r d according to table 15.1. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 15.2 connection of crystal resonator (example) table 15.1 damping resistance value frequency (mhz) 4 8 12 16 20 24 r d ( ? ) 5002000000 rev. 0.5, 03/03, page 355 of 438 figure 15.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 15.2. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 15.3 crystal resonator equivalent circuit table 15.2 crystal resonator characteristics frequency (mhz) 4 8 12 16 20 24 r s max ( ? ) 120 80 60 50 40 40 c 0 max (pf)777777 15.2.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 15.4. if the xtal pin is left open, ensure that stray capacitance does not exceed 10 pf. when complementary clock is input to the xtal pin, the external clock input should be fixed high in standby mode. extal xtal extal xtal external clock input open external clock input (a) xtal pin left open (b) complementary clock input at xtal pin figure 15.4 external clock input (examples) rev. 0.5, 03/03, page 356 of 438 table 15.3 shows the input conditions for the external clock. table 15.3 external clock input conditions v cc = 5.0 v 10% item symbol min. max. unit test conditions external clock input low pulse width t exl 15 ? ns external clock input high pulse width t exh 15 ? ns external clock rise time t exr ?5 ns external clock fall time t exf ?5 ns figure 15.5 0.4 0.6 t cyc 5 mhz clock low pulse width level t cl 80 ? ns < 5 mhz 0.4 0.6 t cyc 5 mhz clock high pulse width level t ch 80 ? ns < 5 mhz figure 18.2 t exh t exl t exr t exf v cc 0.5 extal figure 15.5 external clock input timing rev. 0.5, 03/03, page 357 of 438 15.3 pll circuit the pll circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. the multiplication factor is set by the stc0 bit and the stc1 bit in lpwrcr. the phase of the rising edge of the internal clock is controlled so as to match that at the extal pin. when the multiplication factor of the pll circuit is changed, the operation varies according to the setting of the stcs bit in sckcr. when stcs = 0, the setting becomes valid after a transition to software standby mode. the transition time count is performed in accordance with the setting of bits sts0 to sts2 in sbycr. for details on sbycr, refer to section 16.1.1, standby control register (sbycr). 1. the initial pll circuit multiplication factor is 1. 2. sts0 to sts2 are set to give the specified transition time. 3. the target value is set in stc0 and stc1, and a transition is made to software standby mode. 4. the clock pulse generator stops and the value set in stc0 and stc1 becomes valid. 5. software standby mode is cleared, and a transition time is secured in accordance with the setting in sts0 to sts2. 6. after the set transition time has elapsed, this lsi resumes operation using the target multiplication factor. 15.4 subclock divider the subclock divider divides the clock generated by the oscillator by 128 to generate a subclock. when using the subclock as a system clock, adjustment by software is needed. 15.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 15.6 bus master clock selection circuit the bus master clock selection circuit selects the clock supplied to the bus master by setting the bits sck 2 to 0 in sckcr. the bus master clock can be selected from high-speed mode, or medium-speed clocks ( /2, /4, /8, /16, /32). rev. 0.5, 03/03, page 358 of 438 15.7 usage notes 15.7.1 note on crystal resonator as various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 15.7.2 note on board design when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. other signal lines should be routed away from the oscillator circuit, as shown in figure 15.6. this is to prevent induction from interfering with correct oscillation. c l2 avoid signal a signal b c l1 this lsi xtal extal figure 15.6 note on board design of oscillator circuit figure 15.7 shows external circuitry recommended to be provided around the pll circuit. place oscillation stabilization capacitor c1 and resistor r1 close to the pllcap pin, and ensure that no other signal lines cross this line. separate pllvc l and pllvss from the other vcc and vss lines at the board power supply source, and be sure to insert bypass capacitors cb close to the pins. rev. 0.5, 03/03, page 359 of 438 pllcap pllv cl pllv ss v cc v cl v ss (values are preliminary recommended values.) note: * cb are laminated ceramic. r1 : 3 k c1 : 470 pf cb : 0.1 f cb : 0.1 f * cb : 0.1 f figure 15.7 external circuitry recommended for pll circuit rev. 0.5, 03/03, page 360 of 438 rev. 0.5, 03/03, page 361 of 438 section 16 power-down modes in addition to the normal program execution state, this lsi has eight power-down modes in which operation of the cpu and oscillator is halted and power consumption is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip peripheral modules, and so on. this lsi's operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) subactive mode (4) sleep mode (5) subsleep mode (6) watch mode (7) module stop mode (8) software standby mode (9) hardware standby mode (2) to (9) are power-down modes. sleep and subsleep modes are cpu states, medium-speed mode is a cpu and bus master state, subactive mode is a cpu, bus master, and on-chip peripheral function state, and module stop mode is an on-chip peripheral function (including bus masters other than the cpu) state. some of these states can be combined. after a reset, the lsi is in high-speed mode or module stop mode. figure 16.1 shows a mode transition. table 16.1 shows the conditions of transition between modes when executing the sleep instruction and the state after transition back from low power mode due to an interrupt. table 16.2 shows the internal state of the lsi in each mode. rev. 0.5, 03/03, page 362 of 438 ssby = 0 reset state program-halted state pin = high, pin = low pin = high program execution state sleep command all interrupts interrupts interrupt * 1 , lson bit = 0 interrupt * 1 , lson bit = 1 sleep command sleep command sleep command sleep command external interrupt high-speed mode (main clock) sleep command after the oscillation stabilization time (sts2 to sts0), clock switching exception processing ssby = 1, pss = 1, dton = 1, lson = 0 sleep command clock switching exception processing ssby = 1, pss = 1, dton = 1, lson = 1 ssby = 1 ssby = 1 pss = 1, dton = 0 ssby = 0 pss = 1, lson = 1 * 1 * 2 * 3 * 4 nmi, irq0 to irq5, and wdt_1 interrupts nmi, irq0 to irq5, wdt_0, and wdt_1 interrupts all interrupts nmi and irq0 to irq5 when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs when is driven low. from any state, a transition to hardware standby mode occurs when is driven low. always select high-speed mode before making a transition to watch mode or subactive mode. medium-speed mode (main clock) subactive mode (subclock) subsleep mode (subclock) watch mode (subclock) * 3 * 4 * 2 pin = low hardware standby mode software standby mode sleep mode (main clock) : power-down mode : transition after exception processing notes : sck2 to sck0 = 0 sck2 to sck0 0 figure 16.1 mode transition diagram rev. 0.5, 03/03, page 363 of 438 table 16.1 power-down mode transition conditions status of control bit at transition pre- transition state ssby pss lson dton state after transition invoked by sleep instruction state after transition back from power- down mode invoked by interrupt 0 x 0 x sleep high-speed/medium- speed 0x1 x ?? 1 0 0 x software standby high-speed/medium- speed 101 x ?? 1 1 0 0 watch high-speed 1 1 1 0 watch subactive 110 1 ?? high- speed/ medium- speed 1 1 1 1 subactive ? 00x x ?? 010 x ?? 0 1 1 x subsleep subactive 10x x ?? 1 1 0 0 watch high-speed 1 1 1 0 watch subactive 1 1 0 1 high-speed ? subactive 111 1 ?? legend x: don?t care ? : setting prohibited rev. 0.5, 03/03, page 364 of 438 table 16.2 lsi internal states in each mode function high-speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby system clock pulse generator functioning functioning functioning functioning halted halted halted halted halted cpu instructions registers functioning medium- speed operation halted (retained) high/ medium- speed operation halted (retained) subclock operation halted (retained) halted (retained) halted (undefined) nmi external interrupts irq0 to irq5 functioning functioning functioning functioning functioning functioning functioning functioning halted peripheral functions wdt_0 functioning functioning functioning ? halted (retained) subclock operation subclock operation halted (retained) halted (reset) wdt_1 functioning functioning functioning ? subclock operation subclock operation subclock operation halted (retained) halted (reset) i/o functioning functioning functioning functioning retained functioning retained retained high impedance tpu functioning functioning functioning halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) sci hcan a/d functioning functioning functioning halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) ram functioning medium- speed operation functioning functioning retained functioning retained retained retained notes: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). rev. 0.5, 03/03, page 365 of 438 16.1 register descriptions registers related to the power down mode are shown below. for details on the system clock control register (sckcr), refer to section 15.1.1, system clock control register (sckcr). ? system clock control register (sckcr) ? standby control register (sbycr) ? low-power control register (lpwrcr) ? module stop control register a (mstpcra) ? module stop control register b (mstpcrb) ? module stop control register c (mstpcrc) 16.1.1 standby control register (sbycr) sbycr performs software standby mode control. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit determines the operating mode when a transition is made to power-down mode after executing the sleep instruction according to the combination of the other control bits. 0: shifts to sleep mode when the sleep instruction is executed in high-speed mode or medium-speed mode. shifts to subsleep mode when the sleep instruction is executed in subactive mode. 1: shifts to software standby mode, subactive mode, or watch mode * when the sleep instruction is executed in high-speed mode or medium-speed mode. shifts to watch mode or high-speed mode when the sleep instruction is executed in subactive mode. note: when entering watch mode or subactive mode, the operating mode must be set to high-speed mode. rev. 0.5, 03/03, page 366 of 438 bit bit name initial value r/w description 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 0 to 2 these bits select the mcu wait time for clock stabilization when software standby mode, watch mode, or subactive mode is cancelled by an external interrupt. with a crystal oscillator (table 16.3), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. with an external clock, select a wait time of 2 ms or more. 000: standby time = 8192 states 001: standby time = 16384 states 010: standby time = 32768 states 011: standby time = 65536 states 100: standby time = 131072 states 101: standby time = 262144 states 110: reserved 111: standby time = 16 states 3 ? 1r/wreserved only 1 should be written to this bit. 2 to 0 ? all 0 ? reserved these bits are always read as 0 and cannot be modified. rev. 0.5, 03/03, page 367 of 438 16.1.2 low-power control register (lpwrcr) lpwrcr performs power-down mode control, subclock generation control, oscillation circuit feedback resistance control, and frequency multiplication factor setting. bit bit name initial value r/w description 7 dton 0 r/w direct transition on flag 0: when the sleep instruction is executed in high- speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . when the sleep instruction is executed in subactive mode, operation shifts to subsleep mode or watch mode. 1: when the sleep instruction is executed in high- speed mode or medium-speed mode, operation shifts directly to subactive mode * , or shifts to sleep mode or software standby mode. when the sleep instruction is executed in subactive mode, operation shifts directly to high-speed mode, or shifts to subsleep mode. 6 lson 0 r/w low-speed on flag 0: when the sleep instruction is executed in high- speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . when the sleep instruction is executed in subactive mode, operation shifts to watch mode or shifts directly to high-speed mode. operation shifts to high-speed mode when watch mode is cancelled. 1: when the sleep instruction is executed in high- speed mode, operation shifts to watch mode or subactive mode * . when the sleep instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode. operation shifts to subactive mode when watch mode is cancelled. 5 ? 0r/wreserved this bit can be read from and written to. however, do not write 1 to this bit. 4 substp 0 r/w subclock generation control 0: enables subclock generation 1: disables subclock generation rev. 0.5, 03/03, page 368 of 438 bit bit name initial value r/w description 3 rfcut 0 r/w oscillation circuit feedback resistance control 0: when the main clock is oscillating, sets the feedback resistance on. when the main clock is stopped, sets the feedback resistance off. 1: sets the feedback resistance off. change is valid when software standby mode is entered or after software standby mode is recovered. note: with a crystal resonator, the resonator will not operate if this bit is set to 1. 2 ? 0r/wreserved this bit can be read from and written to. however, do not write 1 to this bit. 1 0 stc1 stc0 0 0 r/w r/w frequency multiplication factor setting these bits specify the frequency multiplication factor of the pll circuit. 00: x1 01: x2 10: x4 11: setting prohibited note: * always set high-speed mode when shifting to watch mode or subactive mode. 16.1.3 module stop control registers a to c (mstpcra to mstpcrc) mstpcr performs module stop mode control. setting a bit to 1 causes the corresponding module to enter module stop mode. clearing the bit to 0 clears the module stop mode. rev. 0.5, 03/03, page 369 of 438 mstpcra bit bit name initial value r/w module 7 mstpa7 * 0r/w 6 mstpa6 * 0r/w 5 mstpa5 1 r/w 16-bit timer pulse unit (tpu) 4 mstpa4 * 1r/w 3 mstpa3 * 1r/w 2 mstpa2 * 1r/w 1 mstpa1 1 r/w a/d converter 0 mstpa0 * 1r/w mstpcrb bit bit name initial value r/w module 7 mstpb7 1 r/w serial communication interface_0 (sci_0) 6 mstpb6 1 r/w serial communication interface_1 (sci_1) 5 mstpb5 1 r/w serial communication interface_2 (sci_2) 4 mstpb4 * 1r/w 3 mstpb3 * 1r/w 2 mstpb2 * 1r/w 1 mstpb1 * 1r/w 0 mstpb0 * 1r/w rev. 0.5, 03/03, page 370 of 438 mstpcrc bit bit name initial value r/w module 7 mstpc7 * 1r/w 6 mstpc6 * 1r/w 5 mstpc5 * 1r/w 4 mstpc4 * 1r/w 3 mstpc3 1 r/w hitachi controller area network (hcan) 2 mstpc2 * 1r/w 1 mstpc1 * 1r/w 0 mstpc0 * 1r/w note: * mstpa7 and mstpa6 are readable/writable bits with an initial value of 0 and should always be written with 0. mstpa4 to mstpa2, mstpa0, mstpb4 to mstpb0, mstpc7 to mstpc4, and mstpc2 to mstpc0 are readable/writable bits with an initial value of 1 and should always be written with 1. 16.2 medium-speed mode when the sck0 to sck2 bits in sckcr are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck0 to sck2 bits. on-chip peripheral modules other than bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck0 to sck2 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is executed with the ssby bit = 1, operation shifts to the software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. rev. 0.5, 03/03, page 371 of 438 when the stby pin is driven low, a transition is made to hardware standby mode. figure 16.2 shows the timing for transition to and clearance of medium-speed mode. sckcr sckcr , peripheral module clock bus master clock internal address bus internal write signal medium-speed mode figure 16.2 medium-speed mode transition and clearance timing 16.3 sleep mode 16.3.1 transition to sleep mode if sleep instruction is executed when the sbycr ssby bit = 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops, however the contents of the cpu's internal registers are retained. other peripheral modules do not stop. 16.3.2 clearing sleep mode sleep mode is cleared by any interrupt, or signals at the res , or stby pins. ? exiting sleep mode by interrupts: when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or if interrupts other than nmi are masked by the cpu. ? exiting sleep mode by res pin: setting the res pin low selects the reset state. after the stipulated reset input duration, driving the res pin high restart the cpu performing reset exception processing. ? exiting sleep mode by stby pin: when the stby pin level is driven low, a transition is made to hardware standby mode. rev. 0.5, 03/03, page 372 of 438 16.4 software standby mode 16.4.1 transition to software standby mode a transition is made to software standby mode if the sleep instruction is executed when the sbycr ssby bit is set to 1. in this mode, the cpu, on-chip peripheral modules, and oscillator, all stop. however, the contents of the cpu's internal registers, on-chip ram data, and the states of on-chip peripheral modules other than the sci, a/d converter, and the states of i/o ports, are retained. in this mode, the oscillator stops, and therefore power consumption is significantly reduced. 16.4.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq5 ), or by means of the res pin or stby pin. ? clearing with an interrupt when an nmi or irq0 to irq5 interrupt request signal is input, clock oscillation starts, and after the time set in bits sts0 to sts2 in sbycr has elapsed, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. when clearing software standby mode with an irq0 to irq5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq5 is generated. software standby mode cannot be cleared if the interrupt has been masked on the cpu side. ? clearing with the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire chip. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. ? clearing with the stby pin when the stby pin is driven low, a transition is made to hardware standby mode. rev. 0.5, 03/03, page 373 of 438 16.4.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. ? using a crystal oscillator set bits sts0 to sts2 so that the standby time is at least 8 ms (the oscillation stabilization time). table 16.3 shows the standby times for different operating frequencies and settings of bits sts0 to sts2. ? using an external clock the pll circuit requires a time for stabilization. set bits sts0 to sts2 so that the standby time is at least 2 ms. table 16.3 oscillation stabilization time settings sts2 sts1 sts0 standby time 24 mhz 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz unit 0 8192 states 0.34 0.41 0.51 0.68 0.8 1.0 1.3 2.0 0 1 16384 states 0.68 0.82 1.0 1.3 1.6 2.0 2.7 4.1 0 32768 states 1.4 1.6 2.0 2.7 3.3 4.1 5.5 8.2 0 1 1 65536 states 2.7 3.3 4.1 5.5 6.6 8.2 10.9 16.4 0 131072 states 5.5 6.6 8.2 10.9 13.1 16.4 21.8 32.8 0 1 262144 states 10.9 13.1 16.4 21.8 26.2 32.8 43.6 65.6 ms 0 reserved ????????? 1 1 1 16 states * 0.7 0.8 1.0 1.3 1.6 2.0 1.7 4.0 s : recommended time setting note: * cannot be set. 16.4.4 software standby mode application example figure 16.3 shows an example in which a transition is made to software standby mode at a falling edge on the nmi pin, and software standby mode is cleared at a rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. rev. 0.5, 03/03, page 374 of 438 oscillator nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 oscillation stabilization time t osc2 software standby mode (power-down mode) nmi exception handling sleep instruction figure 16.3 software standby mode application example 16.5 hardware standby mode 16.5.1 transition to hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md0 to md2) while this lsi is in hardware standby mode. rev. 0.5, 03/03, page 375 of 438 16.5.2 clearing hardware standby mode hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (at least 8 ms?the oscillation stabilization time?when using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 16.5.3 hardware standby mode timings timing of transition to hardware standby mode 1. to retain ram contents with the rame bit set to 1 in syscr drive the res signal low at least 10 states before the stby signal goes low, as shown in figure 16.4. after stby has gone low, res has to wait for at least 0 ns before becoming high. t 2 0ns t 1 10t cyc figure 16.4 timing of transition to hardware standby mode 2. to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained res does not have to be driven low as in the above case. timing of recovery from hardware standby mode drive the res signal low approximately 100 ns or more before stby goes high to execute a power-on reset. t osc1 t 100ns figure 16.5 timing of recovery from hardware standby mode rev. 0.5, 03/03, page 376 of 438 16.6 module stop mode module stop mode can be set for individual on-chip peripheral modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci*, hcan, and a/d converter are retained. after reset clearance, all modules are in module stop mode. when an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. note: the internal states of some sci registers are retained. 16.7 watch mode 16.7.1 transition to watch mode cpu operation makes a transition to watch mode when the sleep instruction is executed in high- speed mode or subactive mode with the ssby bit in sbycr = 1, the dton bit in lpwrcr = 0, and the pss bit in tcsr_1 (wdt_1) = 1. in watch mode, the cpu is stopped and peripheral modules other than wdt_1 are also stopped. the contents of the cpu's internal registers, on-chip ram data, and the states of on-chip peripheral modules other than the sci, hcan, and a/d converter, and the states of i/o ports, are retained. 16.7.2 canceling watch mode watch mode is canceled by any interrupt (wovi1 interrupt, nmi pin, or irq0 to irq5 pin), or signals at the res , or stby pin. canceling watch mode by interrupt: when an interrupt occurs, watch mode is canceled and a transition is made to high-speed mode or medium-speed mode when the lson bit in lpwrcr = 0 or to subactive mode when the lson bit = 1. when a transition is made to high-speed mode, a stable clock is supplied to all lsi circuits and interrupt exception processing starts after the time set in the sts2 to sts0 bits of sbycr has elapsed. in case of an irq0 to irq5 interrupt, watch mode is not canceled if the corresponding enable bit has been cleared to 0. in case of the interrupt rev. 0.5, 03/03, page 377 of 438 from the on-chip peripheral modules, if the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the cpu, watch mode is not canceled. for the setting of the oscillation stabilization time when making a transition from watch mode to high-speed mode, see section 16.4.3, setting oscillation stabilization time after clearing software standby mode. canceling watch mode by res res res res pin: for canceling watch mode by the res pin, see section 16.4.2, clearing software standby mode. canceling watch mode by stby stby stby stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. 16.8 subsleep mode 16.8.1 transition to subsleep mode when the sleep instruction is executed in subactive mode with the ssby bit in sbycr = 0, the lson bit in lpwrcr = 1, and the pss bit in tcsr_1 (wdt_1) = 1, cpu operation shifts to subsleep mode. in subsleep mode, the cpu is stopped and peripheral modules other than wdt_0 and wdt_1 are also stopped. the contents of the cpu's internal registers, on-chip ram data, and the states of on- chip peripheral modules other than the sci, hcan, and a/d converter, and the states of i/o ports, are retained. 16.8.2 canceling subsleep mode subsleep mode is canceled by any interrupt (wovi0 or wovi1 interrupt, nmi pin, or irq0 to irq5 pin), or signals at the res or stby pin. canceling subsleep mode by interrupt: when an interrupt occurs, subsleep mode is canceled and interrupt exception processing starts. in case of an irq0 to irq5 interrupt, subsleep mode is not canceled if the corresponding enable bit has been cleared to 0. in case of the interrupt from the on-chip peripheral modules, if the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the cpu, subsleep mode is not canceled. canceling subsleep mode by res res res res pin: for canceling subsleep mode by the res pin, see section 16.4.2, clearing software standby mode. canceling subsleep mode by stby stby stby stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. rev. 0.5, 03/03, page 378 of 438 16.9 subactive mode 16.9.1 transition to subactive mode cpu operation makes a transition to subactive mode when the sleep instruction is executed in high-speed mode with the ssby bit in sbycr = 1, the dton bit in lpwrcr = 1, the lson bit = 1, and the pss bit in tcsr_1 (wdt_1) = 1. when an interrupt occurs in watch mode, and if the lson bit of lpwrcr is 1, a transition is made to subactive mode. and if an interrupt occurs in subsleep mode, a transition is made to subactive mode. in subactive mode, the cpu operates at low speed on the subclock, and the program is executed one after another. peripheral modules other than wdt_0 and wdt_1 are also stopped. when operating the cpu in subactive mode, the sck2 to sck0 bits in sckcr must be set to 0. 16.9.2 canceling subactive mode subactive mode is canceled by the sleep instruction or signals at the res or stby pin. canceling subactive mode by sleep instruction: when the sleep instruction is executed with the ssby bit in sbycr = 1, the dton bit in lpwrcr = 0, and the pss bit in tcsr_1 (wdt_1) = 1, subactive mode is canceled and a transition is made to watch mode. when the sleep instruction is executed with the ssby bit in sbycr = 0, the lson bit in lpwrcr = 1, and the pss bit in tcsr_1 (wdt_1) = 1, a transition is made to subsleep mode. when the sleep instruction is executed with the ssby bit in sbycr = 1, the dton bit in lpwrcr = 1, the lson bit = 0, and the pss bit in tcsr_1 (wdt_1) = 1, a direct transition is made to high- speed mode (sck0 to sck2 are all 0). canceling subactive mode by res res res res pin: for canceling subactive mode by the res pin, see section 16.4.2, clearing software standby mode. canceling subactive mode by stby stby stby stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. 16.10 direct transitions there are three modes, high-speed, medium-speed, and subactive, in which the cpu executes programs. when a direct transition is made, there is no interruption of program execution in shifting between high-speed and subactive modes. direct transitions are enabled by setting the dton bit in lpwrcr to 1, then executing the sleep instruction. after a transition, direct transition interrupt exception processing starts. rev. 0.5, 03/03, page 379 of 438 16.10.1 direct transitions from high-speed mode to subactive mode execute the sleep instruction in high-speed mode with the ssby bit in sbycr = 1, the lson bit in lpwrcr= 1, the dton bit = 1, and the pss bit in tcsr_1 (wdt_1) = 1, to make a direct transition to subactive mode. 16.10.2 direct transitions from subactive mode to high-speed mode execute the sleep instruction in subactive mode with the ssby bit in sbycr = 1, the lson bit in lpwrcr = 0, the dton bit = 1, and the pss bit in tcsr_1 (wdt_1) = 1, to make a direct transition to high-speed mode after the time set in the sts2 to sts0 bits of sbycr has elapsed. 16.11 clock output disabling function the output of the clock can be controlled by means of the pstop bit in sckcr and ddr for the corresponding port. when the pstop bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. table 16.4 shows the state of the pin in each processing state. table 16.4 pin state in each processing state register settings ddr pstop high-speed mode, medium- speed mode subactive mode sleep mode, subsleep mode software standby mode, watch mode, direct transitions hardware standby mode 0x high impedance high impedance high impedance high impedance high impedance 10 output sub output output fixed high high impedance 1 1 fixed high fixed high fixed high fixed high high impedance legend x: don?t care rev. 0.5, 03/03, page 380 of 438 16.12 usage notes 16.12.1 i/o port status in software standby mode, i/o port states are retained. therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 16.12.2 current consumption during oscillation stabilization wait period current consumption increases during the oscillation stabilization wait period. 16.12.3 on-chip peripheral module interrupt the on-chip peripheral module (tpu), that halts in subactive mode, cannot cancel that interrupt in subactive mode. thus, if a transition is made to subactive mode via watch mode when an interrupt has been requested, it will not be possible to clear the cpu interrupt source. interrupts should therefore be disabled before executing the sleep instruction, then entering watch mode. 16.12.4 writing to mstpcr mstpcr should only be written to by the cpu. rev. 0.5, 03/03, page 381 of 438 section 17 list of registers the address list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified by functional modules. ? the access size is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? no entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 3. register states in each operating mode ? register states are described in the same order as the register addresses. ? the register states described here are for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. rev. 0.5, 03/03, page 382 of 438 17.1 register addresses (address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the specified reference clock. register name abbrevia- tion bit no. address * module data width access state master control register mcr 8 h'f800 hcan 16 4 general status register gsr 8 h'f801 hcan 16 4 bit configuration register bcr 16 h'f802 hcan 16 4 mailbox configuration register mbcr 16 h'f804 hcan 16 4 transmit wait register txpr 16 h'f806 hcan 16 4 transmit wait cancel register txcr 16 h'f808 hcan 16 4 transmit acknowledge register txack 16 h'f80a hcan 16 4 abort acknowledge register aback 16 h'f80c hcan 16 4 receive complete register rxpr 16 h'f80e hcan 16 4 remote request register rfpr 16 h'f810 hcan 16 4 interrupt register irr 16 h'f812 hcan 16 4 mailbox interrupt mask register mbimr 16 h'f814 hcan 16 4 interrupt mask register imr 16 h'f816 hcan 16 4 receive error counter rec 8 h'f818 hcan 16 4 transmit error counter tec 8 h'f819 hcan 16 4 unread message status register umsr 16 h'f81a hcan 16 4 local acceptance filter mask l lafml 16 h'f81c hcan 16 4 local acceptance filter mask h lafmh 16 h'f81e hcan 16 4 message control 0[1] mc0[1] 8 h'f820 hcan 16 4 message control 0[2] mc0[2] 8 h'f821 hcan 16 4 message control 0[3] mc0[3] 8 h'f822 hcan 16 4 message control 0[4] mc0[4] 8 h'f823 hcan 16 4 message control 0[5] mc0[5] 8 h'f824 hcan 16 4 message control 0[6] mc0[6] 8 h'f825 hcan 16 4 message control 0[7] mc0[7] 8 h'f826 hcan 16 4 message control 0[8] mc0[8] 8 h'f827 hcan 16 4 message control 1[1] mc1[1] 8 h'f828 hcan 16 4 rev. 0.5, 03/03, page 383 of 438 register name abbrevia- tion bit no. address * module data width access state message control 1[2] mc1[2] 8 h'f829 hcan 16 4 message control 1[3] mc1[3] 8 h'f82a hcan 16 4 message control 1[4] mc1[4] 8 h'f82b hcan 16 4 message control 1[5] mc1[5] 8 h'f82c hcan 16 4 message control 1[6] mc1[6] 8 h'f82d hcan 16 4 message control 1[7] mc1[7] 8 h'f82e hcan 16 4 message control 1[8] mc1[8] 8 h'f82f hcan 16 4 message control 2[1] mc2[1] 8 h'f830 hcan 16 4 message control 2[2] mc2[2] 8 h'f831 hcan 16 4 message control 2[3] mc2[3] 8 h'f832 hcan 16 4 message control 2[4] mc2[4] 8 h'f833 hcan 16 4 message control 2[5] mc2[5] 8 h'f834 hcan 16 4 message control 2[6] mc2[6] 8 h'f835 hcan 16 4 message control 2[7] mc2[7] 8 h'f836 hcan 16 4 message control 2[8] mc2[8] 8 h'f837 hcan 16 4 message control 3[1] mc3[1] 8 h'f838 hcan 16 4 message control 3[2] mc3[2] 8 h'f839 hcan 16 4 message control 3[3] mc3[3] 8 h'f83a hcan 16 4 message control 3[4] mc3[4] 8 h'f83b hcan 16 4 message control 3[5] mc3[5] 8 h'f83c hcan 16 4 message control 3[6] mc3[6] 8 h'f83d hcan 16 4 message control 3[7] mc3[7] 8 h'f83e hcan 16 4 message control 3[8] mc3[8] 8 h'f83f hcan 16 4 message control 4[1] mc4[1] 8 h'f840 hcan 16 4 message control 4[2] mc4[2] 8 h'f841 hcan 16 4 message control 4[3] mc4[3] 8 h'f842 hcan 16 4 message control 4[4] mc4[4] 8 h'f843 hcan 16 4 message control 4[5] mc4[5] 8 h'f844 hcan 16 4 message control 4[6] mc4[6] 8 h'f845 hcan 16 4 message control 4[7] mc4[7] 8 h'f846 hcan 16 4 message control 4[8] mc4[8] 8 h'f847 hcan 16 4 message control 5[1] mc5[1] 8 h'f848 hcan 16 4 message control 5[2] mc5[2] 8 h'f849 hcan 16 4 rev. 0.5, 03/03, page 384 of 438 register name abbrevia- tion bit no. address * module data width access state message control 5[3] mc5[3] 8 h'f84a hcan 16 4 message control 5[4] mc5[4] 8 h'f84b hcan 16 4 message control 5[5] mc5[5] 8 h'f84c hcan 16 4 message control 5[6] mc5[6] 8 h'f84d hcan 16 4 message control 5[7] mc5[7] 8 h'f84e hcan 16 4 message control 5[8] mc5[8] 8 h'f84f hcan 16 4 message control 6[1] mc6[1] 8 h'f850 hcan 16 4 message control 6[2] mc6[2] 8 h'f851 hcan 16 4 message control 6[3] mc6[3] 8 h'f852 hcan 16 4 message control 6[4] mc6[4] 8 h'f853 hcan 16 4 message control 6[5] mc6[5] 8 h'f854 hcan 16 4 message control 6[6] mc6[6] 8 h'f855 hcan 16 4 message control 6[7] mc6[7] 8 h'f856 hcan 16 4 message control 6[8] mc6[8] 8 h'f857 hcan 16 4 message control 7[1] mc7[1] 8 h'f858 hcan 16 4 message control 7[2] mc7[2] 8 h'f859 hcan 16 4 message control 7[3] mc7[3] 8 h'f85a hcan 16 4 message control 7[4] mc7[4] 8 h'f85b hcan 16 4 message control 7[5] mc7[5] 8 h'f85c hcan 16 4 message control 7[6] mc7[6] 8 h'f85d hcan 16 4 message control 7[7] mc7[7] 8 h'f85e hcan 16 4 message control 7[8] mc7[8] 8 h'f85f hcan 16 4 message control 8[1] mc8[1] 8 h'f860 hcan 16 4 message control 8[2] mc8[2] 8 h'f861 hcan 16 4 message control 8[3] mc8[3] 8 h'f862 hcan 16 4 message control 8[4] mc8[4] 8 h'f863 hcan 16 4 message control 8[5] mc8[5] 8 h'f864 hcan 16 4 message control 8[6] mc8[6] 8 h'f865 hcan 16 4 message control 8[7] mc8[7] 8 h'f866 hcan 16 4 message control 8[8] mc8[8] 8 h'f867 hcan 16 4 message control 9[1] mc9[1] 8 h'f868 hcan 16 4 message control 9[2] mc9[2] 8 h'f869 hcan 16 4 message control 9[3] mc9[3] 8 h'f86a hcan 16 4 rev. 0.5, 03/03, page 385 of 438 register name abbrevia- tion bit no. address * module data width access state message control 9[4] mc9[4] 8 h'f86b hcan 16 4 message control 9[5] mc9[5] 8 h'f86c hcan 16 4 message control 9[6] mc9[6] 8 h'f86d hcan 16 4 message control 9[7] mc9[7] 8 h'f86e hcan 16 4 message control 9[8] mc9[8] 8 h'f86f hcan 16 4 message control 10[1] mc10[1] 8 h'f870 hcan 16 4 message control 10[2] mc10[2] 8 h'f871 hcan 16 4 message control 10[3] mc10[3] 8 h'f872 hcan 16 4 message control 10[4] mc10[4] 8 h'f873 hcan 16 4 message control 10[5] mc10[5] 8 h'f874 hcan 16 4 message control 10[6] mc10[6] 8 h'f875 hcan 16 4 message control 10[7] mc10[7] 8 h'f876 hcan 16 4 message control 10[8] mc10[8] 8 h'f877 hcan 16 4 message control 11[1] mc11[1] 8 h'f878 hcan 16 4 message control 11[2] mc11[2] 8 h'f879 hcan 16 4 message control 11[3] mc11[3] 8 h'f87a hcan 16 4 message control 11[4] mc11[4] 8 h'f87b hcan 16 4 message control 11[5] mc11[5] 8 h'f87c hcan 16 4 message control 11[6] mc11[6] 8 h'f87d hcan 16 4 message control 11[7] mc11[7] 8 h'f87e hcan 16 4 message control 11[8] mc11[8] 8 h'f87f hcan 16 4 message control 12[1] mc12[1] 8 h'f880 hcan 16 4 message control 12[2] mc12[2] 8 h'f881 hcan 16 4 message control 12[3] mc12[3] 8 h'f882 hcan 16 4 message control 12[4] mc12[4] 8 h'f883 hcan 16 4 message control 12[5] mc12[5] 8 h'f884 hcan 16 4 message control 12[6] mc12[6] 8 h'f885 hcan 16 4 message control 12[7] mc12[7] 8 h'f886 hcan 16 4 message control 12[8] mc12[8] 8 h'f887 hcan 16 4 message control 13[1] mc13[1] 8 h'f888 hcan 16 4 message control 13[2] mc13[2] 8 h'f889 hcan 16 4 message control 13[3] mc13[3] 8 h'f88a hcan 16 4 message control 13[4] mc13[4] 8 h'f88b hcan 16 4 rev. 0.5, 03/03, page 386 of 438 register name abbrevia- tion bit no. address * module data width access state message control 13[5] mc13[5] 8 h'f88c hcan 16 4 message control 13[6] mc13[6] 8 h'f88d hcan 16 4 message control 13[7] mc13[7] 8 h'f88e hcan 16 4 message control 13[8] mc13[8] 8 h'f88f hcan 16 4 message control 14[1] mc14[1] 8 h'f890 hcan 16 4 message control 14[2] mc14[2] 8 h'f891 hcan 16 4 message control 14[3] mc14[3] 8 h'f892 hcan 16 4 message control 14[4] mc14[4] 8 h'f893 hcan 16 4 message control 14[5] mc14[5] 8 h'f894 hcan 16 4 message control 14[6] mc14[6] 8 h'f895 hcan 16 4 message control 14[7] mc14[7] 8 h'f896 hcan 16 4 message control 14[8] mc14[8] 8 h'f897 hcan 16 4 message control 15[1] mc15[1] 8 h'f898 hcan 16 4 message control 15[2] mc15[2] 8 h'f899 hcan 16 4 message control 15[3] mc15[3] 8 h'f89a hcan 16 4 message control 15[4] mc15[4] 8 h'f89b hcan 16 4 message control 15[5] mc15[5] 8 h'f89c hcan 16 4 message control 15[6] mc15[6] 8 h'f89d hcan 16 4 message control 15[7] mc15[7] 8 h'f89e hcan 16 4 message control 15[8] mc15[8] 8 h'f89f hcan 16 4 message data 0[1] md0[1] 8 h'f8b0 hcan 16 4 message data 0[2] md0[2] 8 h'f8b1 hcan 16 4 message data 0[3] md0[3] 8 h'f8b2 hcan 16 4 message data 0[4] md0[4] 8 h'f8b3 hcan 16 4 message data 0[5] md0[5] 8 h'f8b4 hcan 16 4 message data 0[6] md0[6] 8 h'f8b5 hcan 16 4 message data 0[7] md0[7] 8 h'f8b6 hcan 16 4 message data 0[8] md0[8] 8 h'f8b7 hcan 16 4 message data 1[1] md1[1] 8 h'f8b8 hcan 16 4 message data 1[2] md1[2] 8 h'f8b9 hcan 16 4 message data 1[3] md1[3] 8 h'f8ba hcan 16 4 message data 1[4] md1[4] 8 h'f8bb hcan 16 4 message data 1[5] md1[5] 8 h'f8bc hcan 16 4 rev. 0.5, 03/03, page 387 of 438 register name abbrevia- tion bit no. address * module data width access state message data 1[6] md1[6] 8 h'f8bd hcan 16 4 message data 1[7] md1[7] 8 h'f8be hcan 16 4 message data 1[8] md1[8] 8 h'f8bf hcan 16 4 message data 2[1] md2[1] 8 h'f8c0 hcan 16 4 message data 2[2] md2[2] 8 h'f8c1 hcan 16 4 message data 2[3] md2[3] 8 h'f8c2 hcan 16 4 message data 2[4] md2[4] 8 h'f8c3 hcan 16 4 message data 2[5] md2[5] 8 h'f8c4 hcan 16 4 message data 2[6] md2[6] 8 h'f8c5 hcan 16 4 message data 2[7] md2[7] 8 h'f8c6 hcan 16 4 message data 2[8] md2[8] 8 h'f8c7 hcan 16 4 message data 3[1] md3[1] 8 h'f8c8 hcan 16 4 message data 3[2] md3[2] 8 h'f8c9 hcan 16 4 message data 3[3] md3[3] 8 h'f8ca hcan 16 4 message data 3[4] md3[4] 8 h'f8cb hcan 16 4 message data 3[5] md3[5] 8 h'f8cc hcan 16 4 message data 3[6] md3[6] 8 h'f8cd hcan 16 4 message data 3[7] md3[7] 8 h'f8ce hcan 16 4 message data 3[8] md3[8] 8 h'f8cf hcan 16 4 message data 4[1] md4[1] 8 h'f8d0 hcan 16 4 message data 4[2] md4[2] 8 h'f8d1 hcan 16 4 message data 4[3] md4[3] 8 h'f8d2 hcan 16 4 message data 4[4] md4[4] 8 h'f8d3 hcan 16 4 message data 4[5] md4[5] 8 h'f8d4 hcan 16 4 message data 4[6] md4[6] 8 h'f8d5 hcan 16 4 message data 4[7] md4[7] 8 h'f8d6 hcan 16 4 message data 4[8] md4[8] 8 h'f8d7 hcan 16 4 message data 5[1] md5[1] 8 h'f8d8 hcan 16 4 message data 5[2] md5[2] 8 h'f8d9 hcan 16 4 message data 5[3] md5[3] 8 h'f8da hcan 16 4 message data 5[4] md5[4] 8 h'f8db hcan 16 4 message data 5[5] md5[5] 8 h'f8dc hcan 16 4 message data 5[6] md5[6] 8 h'f8dd hcan 16 4 rev. 0.5, 03/03, page 388 of 438 register name abbrevia- tion bit no. address * module data width access state message data 5[7] md5[7] 8 h'f8de hcan 16 4 message data 5[8] md5[8] 8 h'f8df hcan 16 4 message data 6[1] md6[1] 8 h'f8e0 hcan 16 4 message data 6[2] md6[2] 8 h'f8e1 hcan 16 4 message data 6[3] md6[3] 8 h'f8e2 hcan 16 4 message data 6[4] md6[4] 8 h'f8e3 hcan 16 4 message data 6[5] md6[5] 8 h'f8e4 hcan 16 4 message data 6[6] md6[6] 8 h'f8e5 hcan 16 4 message data 6[7] md6[7] 8 h'f8e6 hcan 16 4 message data 6[8] md6[8] 8 h'f8e7 hcan 16 4 message data 7[1] md7[1] 8 h'f8e8 hcan 16 4 message data 7[2] md7[2] 8 h'f8e9 hcan 16 4 message data 7[3] md7[3] 8 h'f8ea hcan 16 4 message data 7[4] md7[4] 8 h'f8eb hcan 16 4 message data 7[5] md7[5] 8 h'f8ec hcan 16 4 message data 7[6] md7[6] 8 h'f8ed hcan 16 4 message data 7[7] md7[7] 8 h'f8ee hcan 16 4 message data 7[8] md7[8] 8 h'f8ef hcan 16 4 message data 8[1] md8[1] 8 h'f8f0 hcan 16 4 message data 8[2] md8[2] 8 h'f8f1 hcan 16 4 message data 8[3] md8[3] 8 h'f8f2 hcan 16 4 message data 8[4] md8[4] 8 h'f8f3 hcan 16 4 message data 8[5] md8[5] 8 h'f8f4 hcan 16 4 message data 8[6] md8[6] 8 h'f8f5 hcan 16 4 message data 8[7] md8[7] 8 h'f8f6 hcan 16 4 message data 8[8] md8[8] 8 h'f8f7 hcan 16 4 message data 9[1] md9[1] 8 h'f8f8 hcan 16 4 message data 9[2] md9[2] 8 h'f8f9 hcan 16 4 message data 9[3] md9[3] 8 h'f8fa hcan 16 4 message data 9[4] md9[4] 8 h'f8fb hcan 16 4 message data 9[5] md9[5] 8 h'f8fc hcan 16 4 message data 9[6] md9[6] 8 h'f8fd hcan 16 4 message data 9[7] md9[7] 8 h'f8fe hcan 16 4 message data 9[8] md9[8] 8 h'f8ff hcan 16 4 rev. 0.5, 03/03, page 389 of 438 register name abbrevia- tion bit no. address * module data width access state message data 10[1] md10[1] 8 h'f900 hcan 16 4 message data 10[2] md10[2] 8 h'f901 hcan 16 4 message data 10[3] md10[3] 8 h'f902 hcan 16 4 message data 10[4] md10[4] 8 h'f903 hcan 16 4 message data 10[5] md10[5] 8 h'f904 hcan 16 4 message data 10[6] md10[6] 8 h'f905 hcan 16 4 message data 10[7] md10[7] 8 h'f906 hcan 16 4 message data 10[8] md10[8] 8 h'f907 hcan 16 4 message data 11[1] md11[1] 8 h'f908 hcan 16 4 message data 11[2] md11[2] 8 h'f909 hcan 16 4 message data 11[3] md11[3] 8 h'f90a hcan 16 4 message data 11[4] md11[4] 8 h'f90b hcan 16 4 message data 11[5] md11[5] 8 h'f90c hcan 16 4 message data 11[6] md11[6] 8 h'f90d hcan 16 4 message data 11[7] md11[7] 8 h'f90e hcan 16 4 message data 11[8] md11[8] 8 h'f90f hcan 16 4 message data 12[1] md12[1] 8 h'f910 hcan 16 4 message data 12[2] md12[2] 8 h'f911 hcan 16 4 message data 12[3] md12[3] 8 h'f912 hcan 16 4 message data 12[4] md12[4] 8 h'f913 hcan 16 4 message data 12[5] md12[5] 8 h'f914 hcan 16 4 message data 12[6] md12[6] 8 h'f915 hcan 16 4 message data 12[7] md12[7] 8 h'f916 hcan 16 4 message data 12[8] md12[8] 8 h'f917 hcan 16 4 message data 13[1] md13[1] 8 h'f918 hcan 16 4 message data 13[2] md13[2] 8 h'f919 hcan 16 4 message data 13[3] md13[3] 8 h'f91a hcan 16 4 message data 13[4] md13[4] 8 h'f91b hcan 16 4 message data 13[5] md13[5] 8 h'f91c hcan 16 4 message data 13[6] md13[6] 8 h'f91d hcan 16 4 message data 13[7] md13[7] 8 h'f91e hcan 16 4 message data 13[8] md13[8] 8 h'f91f hcan 16 4 message data 14[1] md14[1] 8 h'f920 hcan 16 4 rev. 0.5, 03/03, page 390 of 438 register name abbrevia- tion bit no. address * module data width access state message data 14[2] md14[2] 8 h'f921 hcan 16 4 message data 14[3] md14[3] 8 h'f922 hcan 16 4 message data 14[4] md14[4] 8 h'f923 hcan 16 4 message data 14[5] md14[5] 8 h'f924 hcan 16 4 message data 14[6] md14[6] 8 h'f925 hcan 16 4 message data 14[7] md14[7] 8 h'f926 hcan 16 4 message data 14[8] md14[8] 8 h'f927 hcan 16 4 message data 15[1] md15[1] 8 h'f928 hcan 16 4 message data 15[2] md15[2] 8 h'f929 hcan 16 4 message data 15[3] md15[3] 8 h'f92a hcan 16 4 message data 15[4] md15[4] 8 h'f92b hcan 16 4 message data 15[5] md15[5] 8 h'f92c hcan 16 4 message data 15[6] md15[6] 8 h'f92d hcan 16 4 message data 15[7] md15[7] 8 h'f92e hcan 16 4 message data 15[8] md15[8] 8 h'f92f hcan 16 4 hcan monitor register hcanmon 8 h'fa00 hcan 16 4 standby control register sbycr 8 h'fde4 system 8 2 system control register syscr 8 h'fde5 system 8 2 system clock control register sckcr 8 h'fde6 system 8 2 mode control register mdcr 8 h'fde7 system 8 2 module stop control register a mstpcra 8 h'fde8 system 8 2 module stop control register b mstpcrb 8 h'fde9 system 8 2 module stop control register c mstpcrc 8 h'fdea system 8 2 low-power control register lpwrcr 8 h'fdec system 8 2 irq sense control register h iscrh 8 h'fe12 int 8 2 irq sense control register l iscrl 8 h'fe13 int 8 2 irq enable register ier 8 h'fe14 int 8 2 irq status register isr 8 h'fe15 int 8 2 port 1 data direction register p1ddr 8 h'fe30 port 8 2 port a data direction register paddr 8 h'fe39 port 8 2 port b data direction register pbddr 8 h'fe3a port 8 2 port c data direction register pcddr 8 h'fe3b port 8 2 port d data direction register pdddr 8 h'fe3c port 8 2 rev. 0.5, 03/03, page 391 of 438 register name abbrevia- tion bit no. address * module data width access state port f data direction register pfddr 8 h'fe3e port 8 2 port a pull-up mos control register papcr 8 h'fe40 port 8 2 port b pull-up mos control register pbpcr 8 h'fe41 port 8 2 port c pull-up mos control register pcpcr 8 h'fe42 port 8 2 port d pull-up mos control register pdpcr 8 h'fe43 port 8 2 port a open drain control register paodr 8 h'fe47 port 8 2 port b open drain control register pbodr 8 h'fe48 port 8 2 port c open drain control register pcodr 8 h'fe49 port 8 2 timer control register_3 tcr_3 8 h'fe80 tpu_3 16 2 timer mode register_3 tmdr_3 8 h'fe81 tpu_3 16 2 timer i/o control register h_3 tiorh_3 8 h'fe82 tpu_3 16 2 timer i/o control register l_3 tiorl_3 8 h'fe83 tpu_3 16 2 timer interrupt enable register_3 tier_3 8 h'fe84 tpu_3 16 2 timer status register_3 tsr_3 8 h'fe85 tpu_3 16 2 timer counter _3 tcnt_3 16 h'fe86 tpu_3 16 2 timer general register a_3 tgra_3 16 h'fe88 tpu_3 16 2 timer general register b_3 tgrb_3 16 h'fe8a tpu_3 16 2 timer general register c_3 tgrc_3 16 h'fe8c tpu_3 16 2 timer general register d_3 tgrd_3 16 h'fe8e tpu_3 16 2 timer control register_4 tcr_4 8 h'fe90 tpu_4 16 2 timer mode register_4 tmdr_4 8 h'fe91 tpu_4 16 2 timer i/o control register_4 tior_4 8 h'fe92 tpu_4 16 2 timer interrupt enable register_4 tier_4 8 h'fe94 tpu_4 16 2 timer status register_4 tsr_4 8 h'fe95 tpu_4 16 2 timer counter_4 tcnt_4 16 h'fe96 tpu_4 16 2 timer general register a_4 tgra_4 16 h'fe98 tpu_4 16 2 timer general register b_4 tgrb_4 16 h'fe9a tpu_4 16 2 timer control register_5 tcr_5 8 h'fea0 tpu_5 16 2 timer mode register_5 tmdr_5 8 h'fea1 tpu_5 16 2 timer i/o control register_5 tior_5 8 h'fea2 tpu_5 16 2 timer interrupt enable register_5 tier_5 8 h'fea4 tpu_5 16 2 timer status register_5 tsr_5 8 h'fea5 tpu_5 16 2 timer counter_5 tcnt_5 16 h'fea6 tpu_5 16 2 rev. 0.5, 03/03, page 392 of 438 register name abbrevia- tion bit no. address * module data width access state timer general register a_5 tgra_5 16 h'fea8 tpu_5 16 2 timer general register b_5 tgrb_5 16 h'feaa tpu_5 16 2 timer start register tstr 8 h'feb0 tpu common 16 2 timer synchro register tsyr 8 h'feb1 tpu common 16 2 interrupt priority register a ipra 8 h'fec0 int 8 2 interrupt priority register b iprb 8 h'fec1 int 8 2 interrupt priority register d iprd 8 h'fec3 int 8 2 interrupt priority register e ipre 8 h'fec4 int 8 2 interrupt priority register f iprf 8 h'fec5 int 8 2 interrupt priority register g iprg 8 h'fec6 int 8 2 interrupt priority register h iprh 8 h'fec7 int 8 2 interrupt priority register j iprj 8 h'fec9 int 8 2 interrupt priority register k iprk 8 h'feca int 8 2 interrupt priority register m iprm 8 h'fecc int 8 2 ram emulation register ramer 8 h'fedb rom 8 2 port 1 data register p1dr 8 h'ff00 port 8 2 port a data register padr 8 h'ff09 port 8 2 port b data register pbdr 8 h'ff0a port 8 2 port c data register pcdr 8 h'ff0b port 8 2 port d data register pddr 8 h'ff0c port 8 2 port f data register pfdr 8 h'ff0e port 8 2 timer control register_0 tcr_0 8 h'ff10 tpu_0 16 2 timer mode register_0 tmdr_0 8 h'ff11 tpu_0 16 2 timer i/o control register h_0 tiorh_0 8 h'ff12 tpu_0 16 2 timer i/o control register l_0 tiorl_0 8 h'ff13 tpu_0 16 2 timer interrupt enable register_0 tier_0 8 h'ff14 tpu_0 16 2 timer status register_0 tsr_0 8 h'ff15 tpu_0 16 2 timer counter_0 tcnt_0 16 h'ff16 tpu_0 16 2 timer general register a_0 tgra_0 16 h'ff18 tpu_0 16 2 timer general register b_0 tgrb_0 16 h'ff1a tpu_0 16 2 timer general register c_0 tgrc_0 16 h'ff1c tpu_0 16 2 rev. 0.5, 03/03, page 393 of 438 register name abbrevia- tion bit no. address * module data width access state timer general register d_0 tgrd_0 16 h'ff1e tpu_0 16 2 timer control register_1 tcr_1 8 h'ff20 tpu_1 16 2 timer mode register_1 tmdr_1 8 h'ff21 tpu_1 16 2 timer i/o control register_1 tior_1 8 h'ff22 tpu_1 16 2 timer interrupt enable register_1 tier_1 8 h'ff24 tpu_1 16 2 timer status register_1 tsr_1 8 h'ff25 tpu_1 16 2 timer counter_1 tcnt_1 16 h'ff26 tpu_1 16 2 timer general register a_1 tgra_1 16 h'ff28 tpu_1 16 2 timer general register b_1 tgrb_1 16 h'ff2a tpu_1 16 2 timer control register_2 tcr_2 8 h'ff30 tpu_2 16 2 timer mode register_2 tmdr_2 8 h'ff31 tpu_2 16 2 timer i/o control register_2 tior_2 8 h'ff32 tpu_2 16 2 timer interrupt enable register_2 tier_2 8 h'ff34 tpu_2 16 2 timer status register_2 tsr_2 8 h'ff35 tpu_2 16 2 timer counter_2 tcnt_2 16 h'ff36 tpu_2 16 2 timer general register a_2 tgra_2 16 h'ff38 tpu_2 16 2 timer general register b_2 tgrb_2 16 h'ff3a tpu_2 16 2 timer control/status register_0 tcsr_0 8 h'ff74 wdt_0 16 2 timer counter_0 tcnt_0 8 h'ff75 wdt_0 16 2 reset control/status register rstcsr 8 h'ff77 wdt_0 16 2 serial mode register_0 smr_0 8 h'ff78 sci_0 8 2 bit rate register_0 brr_0 8 h'ff79 sci_0 8 2 serial control register_0 scr_0 8 h'ff7a sci_0 8 2 transmit data register_0 tdr_0 8 h'ff7b sci_0 8 2 serial status register_0 ssr_0 8 h'ff7c sci_0 8 2 receive data register_0 rdr_0 8 h'ff7d sci_0 8 2 smart card mode register_0 scmr_0 8 h'ff7e sci_0 8 2 serial mode register_1 smr_1 8 h'ff80 sci_1 8 2 bit rate register_1 brr_1 8 h'ff81 sci_1 8 2 serial control register_1 scr_1 8 h'ff82 sci_1 8 2 transmit data register_1 tdr_1 8 h'ff83 sci_1 8 2 serial status register_1 ssr_1 8 h'ff84 sci_1 8 2 receive data register_1 rdr_1 8 h'ff85 sci_1 8 2 rev. 0.5, 03/03, page 394 of 438 register name abbrevia- tion bit no. address * module data width access state smart card mode register_1 scmr_1 8 h'ff86 sci_1 8 2 serial mode register_2 smr_2 8 h'ff88 sci_2 8 2 bit rate register_2 brr_2 8 h'ff89 sci_2 8 2 serial control register_2 scr_2 8 h'ff8a sci_2 8 2 transmit data register_2 tdr_2 8 h'ff8b sci_2 8 2 serial status register_2 ssr_2 8 h'ff8c sci_2 8 2 receive data register_2 rdr_2 8 h'ff8d sci_2 8 2 smart card mode register_2 scmr_2 8 h'ff8e sci_2 8 2 a/d data register ah addrah 8 h?ff90 a/d 8 2 a/d data register al addral 8 h?ff91 a/d 8 2 a/d data register bh addrbh 8 h?ff92 a/d 8 2 a/d data register bl addrbl 8 h?ff93 a/d 8 2 a/d data register ch addrch 8 h?ff94 a/d 8 2 a/d data register cl addrcl 8 h?ff95 a/d 8 2 a/d data register dh addrdh 8 h?ff96 a/d 8 2 a/d data register dl addrdl 8 h?ff97 a/d 8 2 a/d control/status register adcsr 8 h?ff98 a/d 8 2 a/d control register adcr 8 h?ff99 a/d 8 2 timer control/status register_1 tcsr_1 8 h'ffa2 wdt_1 16 2 timer counter_1 tcnt_1 8 h'ffa3 wdt_1 16 2 flash memory control register 1 flmcr1 8 h'ffa8 rom 8 2 flash memory control register 2 flmcr2 8 h'ffa9 rom 8 2 erase block register 1 ebr1 8 h'ffaa rom 8 2 flash memory power control register flpwcr 8 h'ffac rom 8 2 port 1 register port1 8 h'ffb0 port 8 2 port 4 register port4 8 h'ffb3 port 8 2 port 9 register port9 8 h'ffb8 port 8 2 port a register porta 8 h'ffb9 port 8 2 port b register portb 8 h'ffba port 8 2 port c register portc 8 h'ffbb port 8 2 port d register portd 8 h'ffbc port 8 2 port f register portf 8 h'ffbe port 8 2 note: lower 16 bits of the address. rev. 0.5, 03/03, page 395 of 438 17.2 register bits register bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit registers are shown as 2 lines. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mcr mcr7 ? mcr5 ? ? mcr2 mcr1 mcr0 hcan gsr ? ? ? ? gsr3 gsr2 gsr1 gsr0 bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 bcr bcr15 bcr14 bcr13 bcr12 bcr11 bcr10 bcr9 bcr8 mbcr7 mbcr6 mbcr5 mbcr4 mbcr3 mbcr2 mbcr1 ? mbcr mbcr15 mbcr14 mbcr13 mbcr12 mbcr11 mbcr10 mbcr9 mbcr8 txpr7 txpr6 txpr5 txpr4 txpr3 txpr2 txpr1 ? txpr txpr15 txpr14 txpr13 txpr12 txpr11 txpr10 txpr9 txpr8 txcr7 txcr6 txcr5 txcr4 txcr3 txcr2 txcr1 ? txcr txcr15 txcr14 txcr13 txcr12 txcr11 txcr10 txcr9 txcr8 txack7 txack6 txack5 txack4 txack3 txack2 txack1 ? txack txack15 txack14 txack13 txack12 txack11 txack10 txack9 txack8 aback7 aback6 aback5 aback4 aback3 aback2 aback1 ? aback aback15 aback14 aback13 aback12 aback11 aback10 aback9 aback8 rxpr7 rxpr6 rxpr5 rxpr4 rxpr3 rxpr2 rxpr1 rxpr0 rxpr rxpr15 rxpr14 rxpr13 rxpr12 rxpr11 rxpr10 rxpr9 rxpr8 rfpr7 rfpr6 rfpr5 rfpr4 rfpr3 rfpr2 rfpr1 rfpr0 rfpr rfpr15 rfpr14 rfpr13 rfpr12 rfpr11 rfpr10 rfpr9 rfpr8 irr7 irr6 irr5 irr4 irr3 irr2 irr1 irr0 irr ? ? ? irr12 ? ? irr9 irr8 mbimr7 mbimr6 mbimr5 mbimr4 mbimr3 mbimr2 mbimr1 mbimr0 mbimr mbimr15 mbimr14 mbimr13 mbimr12 mbimr11 mbimr10 mbimr9 mbimr8 imr7 imr6 imr5 imr4 imr3 imr2 imr1 ? imr ???imr12??imr9imr8 rec bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tec bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 umsr7 umsr6 umsr5 umsr4 umsr3 umsr2 umsr1 umsr0 umsr umsr15 umsr14 umsr13 umsr12 umsr11 umsr10 umsr9 umsr8 lafml7 lafml6 lafml5 lafml4 lafml3 lafml2 lafml1 lafml0 lafml lafml15 lafml14 lafml13 lafml12 lafml11 lafml10 lafml9 lafml8 lafmh7lafmh6lafmh5???lafmh1lafmh0 lafmh lafmh15 lafmh14 lafmh13 lafmh12 lafmh11 lafmh10 lafmh9 lafmh8 mc0[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc0[2]???????? mc0[3]???????? mc0[4]???????? rev. 0.5, 03/03, page 396 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc0[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 hcan mc0[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc0[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc0[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc1[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc1[2]???????? mc1[3]???????? mc1[4]???????? mc1[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc1[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc1[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc1[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc2[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc2[2]???????? mc2[3]???????? mc2[4]???????? mc2[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc2[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc2[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc2[8] id-15 id-14 id-13 id12 id-11 id-10 id-9 id-8 mc3[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc3[2]???????? mc3[3]???????? mc3[4]???????? mc3[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc3[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc3[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc3[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc4[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc4[2]???????? mc4[3]???????? mc4[4]???????? mc4[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc4[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc4[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc4[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc5[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc5[2]???????? mc5[3]???????? mc5[4]???????? mc5[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc5[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 rev. 0.5, 03/03, page 397 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc5[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 hcan mc5[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc6[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc6[2]???????? mc6[3]???????? mc6[4]???????? mc6[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc6[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc6[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc6[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc7[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc7[2]???????? mc7[3]???????? mc7[4]???????? mc7[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc7[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc7[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc7[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc8[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc8[2]???????? mc8[3]???????? mc8[4]???????? mc8[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc8[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc8[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc8[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc9[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc9[2]???????? mc9[3]???????? mc9[4]???????? mc9[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc9[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc9[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc9[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc10[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc10[2]???????? mc10[3]???????? mc10[4]???????? mc10[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc10[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc10[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc10[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 rev. 0.5, 03/03, page 398 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module mc11[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 hcan mc11[2]???????? mc11[3]???????? mc11[4]???????? mc11[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc11[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc11[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc11[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc12[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc12[2]???????? mc12[3]???????? mc12[4]???????? mc12[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc12[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc12[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc12[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc13[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc13[2]???????? mc13[3]???????? mc13[4]???????? mc13[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc13[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc13[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc13[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc14[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc14[2]???????? mc14[3]???????? mc14[4]???????? mc14[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc14[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc14[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc14[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 mc15[1] ? ? ? ? dlc3 dlc2 dlc1 dlc0 mc15[2]???????? mc15[3]???????? mc15[4]???????? mc15[5] id-20 id-19 id-18 rtr ide ? id-17 id-16 mc15[6] id-28 id-27 id-26 id-25 id-24 id-23 id-22 id-21 mc15[7] id-7 id-6 id-5 id-4 id-3 id-2 id-1 id-0 mc15[8] id-15 id-14 id-13 id-12 id-11 id-10 id-9 id-8 md0[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev. 0.5, 03/03, page 399 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module md0[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcan md0[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md0[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md1[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md2[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md3[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md4[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev. 0.5, 03/03, page 400 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module md5[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcan md5[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md5[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md6[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md7[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md8[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md9[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md10[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev. 0.5, 03/03, page 401 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module md10[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hcan md10[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md11[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md12[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md13[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md14[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[5] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[6] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md15[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev. 0.5, 03/03, page 402 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module hcanmonrxdietxstp????txdrxdhcan sbycr ssby sts2 sts1 sts0 ????system syscr macs ? intm1 intm0 nmieg ? ? rame sckcr pstop ? ? ? stcs sck2 sck1 sck0 mdcr ? ? ? ? ? mds2 mds1 mds0 mstpcra mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 mstpcrb mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 lpwrcr dton lson ? substp rfcut ? stc1 stc0 iscrh ? ? ? ? irq5scb irq5sca irq4scb irq4sca int iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca ier ? ? irq5e irq4e irq3e irq2e irq1e irq0e isr ? ? irq5f irq4f irq3f irq2f irq1f irq0f p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr port paddr ? ? ? ? pa3ddr pa2ddr pa1ddr pa0ddr pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr pdddr pd7ddr pd6ddr pd5ddr pd4ddr ???? pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr papcr ? ? ? ? pa3pcr pa2pcr pa1pcr pa0pcr pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr pdpcrpd7pcrpd6pcrpd5pcrpd4pcr???? paodr ? ? ? ? pa3odr pa2odr pa1odr pa0odr pbodr pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr pcodr pc7odr pc6odr pc5odr pc4odr pc3odr pc2odr pc1odr pc0odr tcr_3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_3 tmdr_3 ? ? bfb bfa md3 md2 md1 md0 tiorh_3 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_3 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_3 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_3 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgra_3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrc_3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrd_3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev. 0.5, 03/03, page 403 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcr_4 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_4 tmdr_4 ? ? ? ? md3 md2 md1 md0 tior_4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_4 ttge ? tcieu tciev ? ? tgieb tgiea tsr_4 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_4 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgra_4 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_4 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcr_5 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_5 tmdr_5 ? ? ? ? md3 md2 md1 md0 tior_5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_5 ttge ? tcieu tciev ? ? tgieb tgiea tsr_5 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_5 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgra_5 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_5 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tstr ? ? cst5 cst4 cst3 cst2 cst1 cst0 tpu common tsyr ? ? sync5 sync4 sync3 sync2 sync1 sync0 ipra ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 int iprb ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprd ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 ipre ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprf ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprg ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprh ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprj ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprk ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 iprm ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 ramer ? ? ? ? rams ram2 ram1 ram0 rom p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr port padr ? ? ? ? pa3dr pa2dr pa1dr pa0dr pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr pddrpd7drpd6drpd5drpd4dr???? pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr rev. 0.5, 03/03, page 404 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcr_0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ? ? bfb bfa md3 md2 md1 md0 tiorh_0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_0 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tpu_0 tgra_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrc_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrd_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcr_1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_1 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu tciev ? ? tgieb tgiea tsr_1 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgra_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tgrb_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcr_2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu_2 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu tciev ? ? tgieb tgiea tsr_2 tcfd ? tcfu tcfv ? ? tgfb tgfa bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 tcnt_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 tgra_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 tgrb_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcsr_0 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt_0 tcnt_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rstcsrwovfrstersts????? rev. 0.5, 03/03, page 405 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module smr_0 * 3 c/ a chr pe o/ e stop mp cks1 cks0 sci_0 (smr_0 * 4 ) (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) (cks1) (cks0) brr_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scr_0 tie rie te re mpie teie cke1 cke0 tdr_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr_0 * 3 tdre rdrf orer fer per tend mpb mpbt (ssr_0 * 4 ) (tdre) (rdrf) (orer) (ers) (per) (tend) (mpb) (mpbt) rdr_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scmr_0????sdirsinv?smif smr_1 * 3 c/ a chr pe o/ e stop mp cks1 cks0 sci_1 (smr_1 * 4 ) (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) (cks1) (cks0) brr_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scr_1 tie rie te re mpie teie cke1 cke0 tdr_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr_1 * 3 tdre rdrf orer fer per tend mpb mpbt (ssr_1 * 4 ) (tdre) (rdrf) (orer) (ers) (per) (tend) (mpb) (mpbt) rdr_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scmr_1????sdirsinv?smif smr_2 * 3 c/ a chr pe o/ e stop mp cks1 cks0 sci_2 (smr_2 * 4 ) (gm) (blk) (pe) (o/ e ) (bcp1) (bcp0) (cks1) (cks0) brr_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scr_2 tie rie te re mpie teie cke1 cke0 tdr_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ssr_2 * 3 tdre rdrf orer fer per tend mpb mpbt (ssr_2 * 4 ) (tdre) (rdrf) (orer) (ers) (per) (tend) (mpb) (mpbt) rdr_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 scmr_2????sdirsinv?smif addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d addral ad1 ad0 ? ????? addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrbl ad1 ad0 ? ????? addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrcl ad1 ad0 ? ????? addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addrdl ad1 ad0 ? ????? adcsr adf adie adst scan ch3 ch2 ch1 ch0 adcr trgs1 trgs0 ? ? cks1 cks0 ? ? tcsr_1 ovf wt/ it tme pss rst/ nmi cks2 cks1 cks0 wdt_1 tcnt_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 flmcr1 fwe swe esu1 psu1 ev1 pv1 e1 p1 rom flmcr2fler??????? ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 flpwcrpdwnd??????? rev. 0.5, 03/03, page 406 of 438 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module port1 p17 p16 p15 p14 p13 p12 p11 p10 port port4 p47 p46 p45 p44 p43 p42 p41 p40 port9 p97 p96 p95 p94 p93 p92 p91 p90 porta ? ? ? ? pa3 pa2 pa1 pa0 portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portdpd7pd6pd5pd4???? portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 notes: 1. for buffer operation. 2. for free operation. 3. normal serial communication interface mode. 4. smart card interface mode. some bit functions of smr differ in normal serial communication interface mode and smart card interface mode. rev. 0.5, 03/03, page 407 of 438 17.3 register states in each operating mode register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module mcr initialized ??? initialized initialized initialized initialized initialized initialized hcan gsr initialized ??? initialized initialized initialized initialized initialized initialized bcr initialized ??? initialized initialized initialized initialized initialized initialized mbcr initialized ??? initialized initialized initialized initialized initialized initialized txpr initialized ??? initialized initialized initialized initialized initialized initialized txcr initialized ??? initialized initialized initialized initialized initialized initialized txack initialized ??? initialized initialized initialized initialized initialized initialized aback initialized ??? initialized initialized initialized initialized initialized initialized rxpr initialized ??? initialized initialized initialized initialized initialized initialized rfpr initialized ??? initialized initialized initialized initialized initialized initialized irr initialized ??? initialized initialized initialized initialized initialized initialized mbimr initialized ??? initialized initialized initialized initialized initialized initialized imr initialized ??? initialized initialized initialized initialized initialized initialized rec initialized ??? initialized initialized initialized initialized initialized initialized tec initialized ??? initialized initialized initialized initialized initialized initialized umsr initialized ??? initialized initialized initialized initialized initialized initialized lafml initialized ??? initialized initialized initialized initialized initialized initialized lafmh initialized ??? initialized initialized initialized initialized initialized initialized mc0[1] initialized ??? initialized initialized initialized initialized initialized initialized mc0[2] initialized ??? initialized initialized initialized initialized initialized initialized mc0[3] initialized ??? initialized initialized initialized initialized initialized initialized mc0[4] initialized ??? initialized initialized initialized initialized initialized initialized mc0[5] initialized ??? initialized initialized initialized initialized initialized initialized mc0[6] initialized ??? initialized initialized initialized initialized initialized initialized mc0[7] initialized ??? initialized initialized initialized initialized initialized initialized mc0[8] initialized ??? initialized initialized initialized initialized initialized initialized mc1[1] initialized ??? initialized initialized initialized initialized initialized initialized mc1[2] initialized ??? initialized initialized initialized initialized initialized initialized mc1[3] initialized ??? initialized initialized initialized initialized initialized initialized mc1[4] initialized ??? initialized initialized initialized initialized initialized initialized mc1[5] initialized ??? initialized initialized initialized initialized initialized initialized mc1[6] initialized ??? initialized initialized initialized initialized initialized initialized mc1[7] initialized ??? initialized initialized initialized initialized initialized initialized mc1[8] initialized ??? initialized initialized initialized initialized initialized initialized mc2[1] initialized ??? initialized initialized initialized initialized initialized initialized mc2[2] initialized ??? initialized initialized initialized initialized initialized initialized mc2[3] initialized ??? initialized initialized initialized initialized initialized initialized mc2[4] initialized ??? initialized initialized initialized initialized initialized initialized mc2[5] initialized ??? initialized initialized initialized initialized initialized initialized mc2[6] initialized ??? initialized initialized initialized initialized initialized initialized mc2[7] initialized ??? initialized initialized initialized initialized initialized initialized mc2[8] initialized ??? initialized initialized initialized initialized initialized initialized mc3[1] initialized ??? initialized initialized initialized initialized initialized initialized mc3[2] initialized ??? initialized initialized initialized initialized initialized initialized mc3[3] initialized ??? initialized initialized initialized initialized initialized initialized mc3[4] initialized ??? initialized initialized initialized initialized initialized initialized mc3[5] initialized ??? initialized initialized initialized initialized initialized initialized rev. 0.5, 03/03, page 408 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module mc3[6] initialized ??? initialized initialized initialized initialized initialized initialized hcan mc3[7] initialized ??? initialized initialized initialized initialized initialized initialized mc3[8] initialized ??? initialized initialized initialized initialized initialized initialized mc4[1] initialized ??? initialized initialized initialized initialized initialized initialized mc4[2] initialized ??? initialized initialized initialized initialized initialized initialized mc4[3] initialized ??? initialized initialized initialized initialized initialized initialized mc4[4] initialized ??? initialized initialized initialized initialized initialized initialized mc4[5] initialized ??? initialized initialized initialized initialized initialized initialized mc4[6] initialized ??? initialized initialized initialized initialized initialized initialized mc4[7] initialized ??? initialized initialized initialized initialized initialized initialized mc4[8] initialized ??? initialized initialized initialized initialized initialized initialized mc5[1] initialized ??? initialized initialized initialized initialized initialized initialized mc5[2] initialized ??? initialized initialized initialized initialized initialized initialized mc5[3] initialized ??? initialized initialized initialized initialized initialized initialized mc5[4] initialized ??? initialized initialized initialized initialized initialized initialized mc5[5] initialized ??? initialized initialized initialized initialized initialized initialized mc5[6] initialized ??? initialized initialized initialized initialized initialized initialized mc5[7] initialized ??? initialized initialized initialized initialized initialized initialized mc5[8] initialized ??? initialized initialized initialized initialized initialized initialized mc6[1] initialized ??? initialized initialized initialized initialized initialized initialized mc6[2] initialized ??? initialized initialized initialized initialized initialized initialized mc6[3] initialized ??? initialized initialized initialized initialized initialized initialized mc6[4] initialized ??? initialized initialized initialized initialized initialized initialized mc6[5] initialized ??? initialized initialized initialized initialized initialized initialized mc6[6] initialized ??? initialized initialized initialized initialized initialized initialized mc6[7] initialized ??? initialized initialized initialized initialized initialized initialized mc6[8] initialized ??? initialized initialized initialized initialized initialized initialized mc7[1] initialized ??? initialized initialized initialized initialized initialized initialized mc7[2] initialized ??? initialized initialized initialized initialized initialized initialized mc7[3] initialized ??? initialized initialized initialized initialized initialized initialized mc7[4] initialized ??? initialized initialized initialized initialized initialized initialized mc7[5] initialized ??? initialized initialized initialized initialized initialized initialized mc7[6] initialized ??? initialized initialized initialized initialized initialized initialized mc7[7] initialized ??? initialized initialized initialized initialized initialized initialized mc7[8] initialized ??? initialized initialized initialized initialized initialized initialized mc8[1] initialized ??? initialized initialized initialized initialized initialized initialized mc8[2] initialized ??? initialized initialized initialized initialized initialized initialized mc8[3] initialized ??? initialized initialized initialized initialized initialized initialized mc8[4] initialized ??? initialized initialized initialized initialized initialized initialized mc8[5] initialized ??? initialized initialized initialized initialized initialized initialized mc8[6] initialized ??? initialized initialized initialized initialized initialized initialized mc8[7] initialized ??? initialized initialized initialized initialized initialized initialized mc8[8] initialized ??? initialized initialized initialized initialized initialized initialized mc9[1] initialized ??? initialized initialized initialized initialized initialized initialized mc9[2] initialized ??? initialized initialized initialized initialized initialized initialized mc9[3] initialized ??? initialized initialized initialized initialized initialized initialized mc9[4] initialized ??? initialized initialized initialized initialized initialized initialized mc9[5] initialized ??? initialized initialized initialized initialized initialized initialized mc9[6] initialized ??? initialized initialized initialized initialized initialized initialized mc9[7] initialized ??? initialized initialized initialized initialized initialized initialized rev. 0.5, 03/03, page 409 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module mc9[8] initialized ??? initialized initialized initialized initialized initialized initialized hcan mc10[1] initialized ??? initialized initialized initialized initialized initialized initialized mc10[2] initialized ??? initialized initialized initialized initialized initialized initialized mc10[3] initialized ??? initialized initialized initialized initialized initialized initialized mc10[4] initialized ??? initialized initialized initialized initialized initialized initialized mc10[5] initialized ??? initialized initialized initialized initialized initialized initialized mc10[6] initialized ??? initialized initialized initialized initialized initialized initialized mc10[7] initialized ??? initialized initialized initialized initialized initialized initialized mc10[8] initialized ??? initialized initialized initialized initialized initialized initialized mc11[1] initialized ??? initialized initialized initialized initialized initialized initialized mc11[2] initialized ??? initialized initialized initialized initialized initialized initialized mc11[3] initialized ??? initialized initialized initialized initialized initialized initialized mc11[4] initialized ??? initialized initialized initialized initialized initialized initialized mc11[5] initialized ??? initialized initialized initialized initialized initialized initialized mc11[6] initialized ??? initialized initialized initialized initialized initialized initialized mc11[7] initialized ??? initialized initialized initialized initialized initialized initialized mc11[8] initialized ??? initialized initialized initialized initialized initialized initialized mc12[1] initialized ??? initialized initialized initialized initialized initialized initialized mc12[2] initialized ??? initialized initialized initialized initialized initialized initialized mc12[3] initialized ??? initialized initialized initialized initialized initialized initialized mc12[4] initialized ??? initialized initialized initialized initialized initialized initialized mc12[5] initialized ??? initialized initialized initialized initialized initialized initialized mc12[6] initialized ??? initialized initialized initialized initialized initialized initialized mc12[7] initialized ??? initialized initialized initialized initialized initialized initialized mc12[8] initialized ??? initialized initialized initialized initialized initialized initialized mc13[1] initialized ??? initialized initialized initialized initialized initialized initialized mc13[2] initialized ??? initialized initialized initialized initialized initialized initialized mc13[3] initialized ??? initialized initialized initialized initialized initialized initialized mc13[4] initialized ??? initialized initialized initialized initialized initialized initialized mc13[5] initialized ??? initialized initialized initialized initialized initialized initialized mc13[6] initialized ??? initialized initialized initialized initialized initialized initialized mc13[7] initialized ??? initialized initialized initialized initialized initialized initialized mc13[8] initialized ??? initialized initialized initialized initialized initialized initialized mc14[1] initialized ??? initialized initialized initialized initialized initialized initialized mc14[2] initialized ??? initialized initialized initialized initialized initialized initialized mc14[3] initialized ??? initialized initialized initialized initialized initialized initialized mc14[4] initialized ??? initialized initialized initialized initialized initialized initialized mc14[5] initialized ??? initialized initialized initialized initialized initialized initialized mc14[6] initialized ??? initialized initialized initialized initialized initialized initialized mc14[7] initialized ??? initialized initialized initialized initialized initialized initialized mc14[8] initialized ??? initialized initialized initialized initialized initialized initialized mc15[1] initialized ??? initialized initialized initialized initialized initialized initialized mc15[2] initialized ??? initialized initialized initialized initialized initialized initialized mc15[3] initialized ??? initialized initialized initialized initialized initialized initialized mc15[4] initialized ??? initialized initialized initialized initialized initialized initialized mc15[5] initialized ??? initialized initialized initialized initialized initialized initialized mc15[6] initialized ??? initialized initialized initialized initialized initialized initialized mc15[7] initialized ??? initialized initialized initialized initialized initialized initialized mc15[8] initialized ??? initialized initialized initialized initialized initialized initialized md0[1] initialized ??? initialized initialized initialized initialized initialized initialized rev. 0.5, 03/03, page 410 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module md0[2] initialized ??? initialized initialized initialized initialized initialized initialized hcan md0[3] initialized ??? initialized initialized initialized initialized initialized initialized md0[4] initialized ??? initialized initialized initialized initialized initialized initialized md0[5] initialized ??? initialized initialized initialized initialized initialized initialized md0[6] initialized ??? initialized initialized initialized initialized initialized initialized md0[7] initialized ??? initialized initialized initialized initialized initialized initialized md0[8] initialized ??? initialized initialized initialized initialized initialized initialized md1[1] initialized ??? initialized initialized initialized initialized initialized initialized md1[2] initialized ??? initialized initialized initialized initialized initialized initialized md1[3] initialized ??? initialized initialized initialized initialized initialized initialized md1[4] initialized ??? initialized initialized initialized initialized initialized initialized md1[5] initialized ??? initialized initialized initialized initialized initialized initialized md1[6] initialized ??? initialized initialized initialized initialized initialized initialized md1[7] initialized ??? initialized initialized initialized initialized initialized initialized md1[8] initialized ??? initialized initialized initialized initialized initialized initialized md2[1] initialized ??? initialized initialized initialized initialized initialized initialized md2[2] initialized ??? initialized initialized initialized initialized initialized initialized md2[3] initialized ??? initialized initialized initialized initialized initialized initialized md2[4] initialized ??? initialized initialized initialized initialized initialized initialized md2[5] initialized ??? initialized initialized initialized initialized initialized initialized md2[6] initialized ??? initialized initialized initialized initialized initialized initialized md2[7] initialized ??? initialized initialized initialized initialized initialized initialized md2[8] initialized ??? initialized initialized initialized initialized initialized initialized md3[1] initialized ??? initialized initialized initialized initialized initialized initialized md3[2] initialized ??? initialized initialized initialized initialized initialized initialized md3[3] initialized ??? initialized initialized initialized initialized initialized initialized md3[4] initialized ??? initialized initialized initialized initialized initialized initialized md3[5] initialized ??? initialized initialized initialized initialized initialized initialized md3[6] initialized ??? initialized initialized initialized initialized initialized initialized md3[7] initialized ??? initialized initialized initialized initialized initialized initialized md3[8] initialized ??? initialized initialized initialized initialized initialized initialized md4[1] initialized ??? initialized initialized initialized initialized initialized initialized md4[2] initialized ??? initialized initialized initialized initialized initialized initialized md4[3] initialized ??? initialized initialized initialized initialized initialized initialized md4[4] initialized ??? initialized initialized initialized initialized initialized initialized md4[5] initialized ??? initialized initialized initialized initialized initialized initialized md4[6] initialized ??? initialized initialized initialized initialized initialized initialized md4[7] initialized ??? initialized initialized initialized initialized initialized initialized md4[8] initialized ??? initialized initialized initialized initialized initialized initialized md5[1] initialized ??? initialized initialized initialized initialized initialized initialized md5[2] initialized ??? initialized initialized initialized initialized initialized initialized md5[3] initialized ??? initialized initialized initialized initialized initialized initialized md5[4] initialized ??? initialized initialized initialized initialized initialized initialized md5[5] initialized ??? initialized initialized initialized initialized initialized initialized md5[6] initialized ??? initialized initialized initialized initialized initialized initialized md5[7] initialized ??? initialized initialized initialized initialized initialized initialized md5[8] initialized ??? initialized initialized initialized initialized initialized initialized md6[1] initialized ??? initialized initialized initialized initialized initialized initialized md6[2] initialized ??? initialized initialized initialized initialized initialized initialized md6[3] initialized ??? initialized initialized initialized initialized initialized initialized rev. 0.5, 03/03, page 411 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module md6[4] initialized ??? initialized initialized initialized initialized initialized initialized hcan md6[5] initialized ??? initialized initialized initialized initialized initialized initialized md6[6] initialized ??? initialized initialized initialized initialized initialized initialized md6[7] initialized ??? initialized initialized initialized initialized initialized initialized md6[8] initialized ??? initialized initialized initialized initialized initialized initialized md7[1] initialized ??? initialized initialized initialized initialized initialized initialized md7[2] initialized ??? initialized initialized initialized initialized initialized initialized md7[3] initialized ??? initialized initialized initialized initialized initialized initialized md7[4] initialized ??? initialized initialized initialized initialized initialized initialized md7[5] initialized ??? initialized initialized initialized initialized initialized initialized md7[6] initialized ??? initialized initialized initialized initialized initialized initialized md7[7] initialized ??? initialized initialized initialized initialized initialized initialized md7[8] initialized ??? initialized initialized initialized initialized initialized initialized md8[1] initialized ??? initialized initialized initialized initialized initialized initialized md8[2] initialized ??? initialized initialized initialized initialized initialized initialized md8[3] initialized ??? initialized initialized initialized initialized initialized initialized md8[4] initialized ??? initialized initialized initialized initialized initialized initialized md8[5] initialized ??? initialized initialized initialized initialized initialized initialized md8[6] initialized ??? initialized initialized initialized initialized initialized initialized md8[7] initialized ??? initialized initialized initialized initialized initialized initialized md8[8] initialized ??? initialized initialized initialized initialized initialized initialized md9[1] initialized ??? initialized initialized initialized initialized initialized initialized md9[2] initialized ??? initialized initialized initialized initialized initialized initialized md9[3] initialized ??? initialized initialized initialized initialized initialized initialized md9[4] initialized ??? initialized initialized initialized initialized initialized initialized md9[5] initialized ??? initialized initialized initialized initialized initialized initialized md9[6] initialized ??? initialized initialized initialized initialized initialized initialized md9[7] initialized ??? initialized initialized initialized initialized initialized initialized md9[8] initialized ??? initialized initialized initialized initialized initialized initialized md10[1] initialized ??? initialized initialized initialized initialized initialized initialized md10[2] initialized ??? initialized initialized initialized initialized initialized initialized md10[3] initialized ??? initialized initialized initialized initialized initialized initialized md10[4] initialized ??? initialized initialized initialized initialized initialized initialized md10[5] initialized ??? initialized initialized initialized initialized initialized initialized md10[6] initialized ??? initialized initialized initialized initialized initialized initialized md10[7] initialized ??? initialized initialized initialized initialized initialized initialized md10[8] initialized ??? initialized initialized initialized initialized initialized initialized md11[1] initialized ??? initialized initialized initialized initialized initialized initialized md11[2] initialized ??? initialized initialized initialized initialized initialized initialized md11[3] initialized ??? initialized initialized initialized initialized initialized initialized md11[4] initialized ??? initialized initialized initialized initialized initialized initialized md11[5] initialized ??? initialized initialized initialized initialized initialized initialized md11[6] initialized ??? initialized initialized initialized initialized initialized initialized md11[7] initialized ??? initialized initialized initialized initialized initialized initialized md11[8] initialized ??? initialized initialized initialized initialized initialized initialized md12[1] initialized ??? initialized initialized initialized initialized initialized initialized md12[2] initialized ??? initialized initialized initialized initialized initialized initialized md12[3] initialized ??? initialized initialized initialized initialized initialized initialized md12[4] initialized ??? initialized initialized initialized initialized initialized initialized md12[5] initialized ??? initialized initialized initialized initialized initialized initialized rev. 0.5, 03/03, page 412 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module md12[6] initialized ??? initialized initialized initialized initialized initialized initialized hcan md12[7] initialized ??? initialized initialized initialized initialized initialized initialized md12[8] initialized ??? initialized initialized initialized initialized initialized initialized md13[1] initialized ??? initialized initialized initialized initialized initialized initialized md13[2] initialized ??? initialized initialized initialized initialized initialized initialized md13[3] initialized ??? initialized initialized initialized initialized initialized initialized md13[4] initialized ??? initialized initialized initialized initialized initialized initialized md13[5] initialized ??? initialized initialized initialized initialized initialized initialized md13[6] initialized ??? initialized initialized initialized initialized initialized initialized md13[7] initialized ??? initialized initialized initialized initialized initialized initialized md13[8] initialized ??? initialized initialized initialized initialized initialized initialized md14[1] initialized ??? initialized initialized initialized initialized initialized initialized md14[2] initialized ??? initialized initialized initialized initialized initialized initialized md14[3] initialized ??? initialized initialized initialized initialized initialized initialized md14[4] initialized ??? initialized initialized initialized initialized initialized initialized md14[5] initialized ??? initialized initialized initialized initialized initialized initialized md14[6] initialized ??? initialized initialized initialized initialized initialized initialized md14[7] initialized ??? initialized initialized initialized initialized initialized initialized md14[8] initialized ??? initialized initialized initialized initialized initialized initialized md15[1] initialized ??? initialized initialized initialized initialized initialized initialized md15[2] initialized ??? initialized initialized initialized initialized initialized initialized md15[3] initialized ??? initialized initialized initialized initialized initialized initialized md15[4] initialized ??? initialized initialized initialized initialized initialized initialized md15[5] initialized ??? initialized initialized initialized initialized initialized initialized md15[6] initialized ??? initialized initialized initialized initialized initialized initialized md15[7] initialized ??? initialized initialized initialized initialized initialized initialized md15[8] initialized ??? initialized initialized initialized initialized initialized initialized hcanmon initialized ??? initialized initialized initialized initialized initialized initialized sbycr initialized ???????? initialized system syscr initialized ???????? initialized sckcr initialized ???????? initialized mdcr initialized ???????? initialized mstpcra initialized ???????? initialized mstpcrb initialized ???????? initialized mstpcrc initialized ???????? initialized lpwrcr initialized ???????? initialized iscrh initialized ???????? initialized int iscrl initialized ???????? initialized ier initialized ???????? initialized isr initialized ???????? initialized p1ddr initialized ???????? initialized port paddr initialized ???????? initialized pbddr initialized ???????? initialized pcddr initialized ???????? initialized pdddr initialized ???????? initialized pfddr initialized ???????? initialized papcr initialized ???????? initialized pbpcr initialized ???????? initialized pcpcr initialized ???????? initialized pdpcr initialized ???????? initialized rev. 0.5, 03/03, page 413 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module paodr initialized ???????? initialized port pbodr initialized ???????? initialized pcodr initialized ???????? initialized tcr_3 initialized ???????? initialized tpu_3 tmdr_3 initialized ???????? initialized tiorh_3 initialized ???????? initialized tiorl_3 initialized ???????? initialized tier_3 initialized ???????? initialized tsr_3 initialized ???????? initialized tcnt_3 initialized ???????? initialized tgra_3 initialized ???????? initialized tgrb_3 initialized ???????? initialized tgrc_3 initialized ???????? initialized tgrd_3 initialized ???????? initialized tcr_4 initialized ???????? initialized tpu_4 tmdr_4 initialized ???????? initialized tior_4 initialized ???????? initialized tier_4 initialized ???????? initialized tsr_4 initialized ???????? initialized tcnt_4 initialized ???????? initialized tgra_4 initialized ???????? initialized tgrb_4 initialized ???????? initialized tcr_5 initialized ???????? initialized tpu_5 tmdr_5 initialized ???????? initialized tior_5 initialized ???????? initialized tier_5 initialized ???????? initialized tsr_5 initialized ???????? initialized tcnt_5 initialized ???????? initialized tgra_5 initialized ???????? initialized tgrb_5 initialized ???????? initialized tstr initialized ???????? initialized tpu common tsyr initialized ???????? initialized ipra initialized ???????? initialized int iprb initialized ???????? initialized iprd initialized ???????? initialized ipre initialized ???????? initialized iprf initialized ???????? initialized iprg initialized ???????? initialized iprh initialized ???????? initialized iprj initialized ???????? initialized iprk initialized ???????? initialized iprm initialized ???????? initialized ramer initialized ???????? initialized rom p1dr initialized ???????? initialized port padr initialized ???????? initialized pbdr initialized ???????? initialized pcdr initialized ???????? initialized pddr initialized ???????? initialized pfdr initialized ???????? initialized rev. 0.5, 03/03, page 414 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module tcr_0 initialized ???????? initialized tpu_0 tmdr_0 initialized ???????? initialized tiorh_0 initialized ???????? initialized tiorl_0 initialized ???????? initialized tier_0 initialized ???????? initialized tsr_0 initialized ???????? initialized tcnt_0 initialized ???????? initialized tgra_0 initialized ???????? initialized tgrb_0 initialized ???????? initialized tgrc_0 initialized ???????? initialized tgrd_0 initialized ???????? initialized tcr_1 initialized ???????? initialized tpu_1 tmdr_1 initialized ???????? initialized tior_1 initialized ???????? initialized tier_1 initialized ???????? initialized tsr_1 initialized ???????? initialized tcnt_1 initialized ???????? initialized tgra_1 initialized ???????? initialized tgrb_1 initialized ???????? initialized tcr_2 initialized ???????? initialized tpu_2 tmdr_2 initialized ???????? initialized tior_2 initialized ???????? initialized tier_2 initialized ???????? initialized tsr_2 initialized ???????? initialized tcnt_2 initialized ???????? initialized tgra_2 initialized ???????? initialized tgrb_2 initialized ???????? initialized tcsr_0 initialized ???????? initialized wdt_0 tcnt_0 initialized ???????? initialized rstcsr initialized ???????? initialized smr_0 initialized ??? initialized initialized initialized initialized initialized initialized sci_0 brr_0 initialized ??? initialized initialized initialized initialized initialized initialized scr_0 initialized ??? initialized initialized initialized initialized initialized initialized tdr_0 initialized ??? initialized initialized initialized initialized initialized initialized ssr_0 initialized ??? initialized initialized initialized initialized initialized initialized rdr_0 initialized ??? initialized initialized initialized initialized initialized initialized scmr_0 initialized ??? initialized initialized initialized initialized initialized initialized smr_1 initialized ??? initialized initialized initialized initialized initialized initialized sci_1 brr_1 initialized ??? initialized initialized initialized initialized initialized initialized scr_1 initialized ??? initialized initialized initialized initialized initialized initialized tdr_1 initialized ??? initialized initialized initialized initialized initialized initialized ssr_1 initialized ??? initialized initialized initialized initialized initialized initialized rdr_1 initialized ??? initialized initialized initialized initialized initialized initialized scmr_1 initialized ??? initialized initialized initialized initialized initialized initialized smr_2 initialized ??? initialized initialized initialized initialized initialized initialized sci_2 brr_2 initialized ??? initialized initialized initialized initialized initialized initialized scr_2 initialized ??? initialized initialized initialized initialized initialized initialized tdr_2 initialized ??? initialized initialized initialized initialized initialized initialized ssr_2 initialized ??? initialized initialized initialized initialized initialized initialized rdr_2 initialized ??? initialized initialized initialized initialized initialized initialized rev. 0.5, 03/03, page 415 of 438 register name reset high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby module scmr_2 initialized ??? initialized initialized initialized initialized initialized initialized sci_2 addrah initialized ??? initialized initialized initialized initialized initialized initialized a/d addral initialized ??? initialized initialized initialized initialized initialized initialized addrbh initialized ??? initialized initialized initialized initialized initialized initialized addrbl initialized ??? initialized initialized initialized initialized initialized initialized addrch initialized ??? initialized initialized initialized initialized initialized initialized addrcl initialized ??? initialized initialized initialized initialized initialized initialized addrdh initialized ??? initialized initialized initialized initialized initialized initialized addrdl initialized ??? initialized initialized initialized initialized initialized initialized adcsr initialized ??? initialized initialized initialized initialized initialized initialized adcr initialized ??? initialized initialized initialized initialized initialized initialized tcsr_1 initialized ???? ???? initialized wdt_1 tcnt_1 initialized ???? ???? initialized flmcr1 initialized ???? ???? initialized rom flmcr2 initialized ???? ???? initialized ebr1 initialized ???? ???? initialized flpwcr initialized ???? ???? initialized port1 initialized ???? ???? initialized port port4 initialized ???? ???? initialized port9 initialized ???? ???? initialized porta initialized ???? ???? initialized portb initialized ???? ???? initialized portc initialized ???? ???? initialized portd initialized ???? ???? initialized portf initialized ???? ???? initialized note: ? is not initialized. rev. 0.5, 03/03, page 416 of 438 rev. 0.5, 03/03, page 417 of 438 section 18 electrical characteristics 18.1 absolute maximum ratings table 18.1 lists the absolute maximum ratings. table 18.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v input voltage (xtal, extal) v in ?0.3 to v cc +0.3 v input voltage (port 4 and 9) v in ?0.3 to av cc +0.3 v input voltage (except xtal, extal, port 4 and 9) v in ?0.3 to v cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded. rev. 0.5, 03/03, page 418 of 438 18.2 dc characteristics table 18.2 lists the dc characteristics. table 18.3 lists the permissible output currents. table 18.2 dc characteristics conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. max. unit test conditions irq0 to irq5 v t ? v cc 0.2??v v t + ??v cc 0.7 v schmitt trigger input voltage v t + ? v t ? v cc 0.05 ? ? v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 v port 1, a to d, f, hrxd v cc 0.7 ? v cc + 0.3 v port 4 and 9 av cc 0.7 ? av cc + 0.3 v input low voltage res , stby , nmi, md2 to md0, fwe v il ?0.3 ? v cc 0.1 v extal ?0.3 ? v cc 0.2 v port 1, a to d, f, hrxd ?0.3 ? v cc 0.2 v port 4, 9 ?0.3 ? av cc 0.2 v all output pins v oh v cc ? 0.5 ? ? v i oh = ?200 a output high voltage v cc ? 1.0 ? ? v i oh = ?1 ma output low voltage all output pins v ol ??0.4vi ol = 1.6 ma res | i in | ? ? 1.0 a v in = 0.5 to input leakage current stby , nmi, md2 to md0, fwe, hrxd ??1.0av cc ? 0.5 v port 4, 9 ? ? 1.0 a v in = 0.5 to av cc ? 0.5 v rev. 0.5, 03/03, page 419 of 438 item symbol min. typ. max. unit test conditions mos input pull-up current port a to d ?i p 30 ? 300 a v in = 0 v res c in ? ? 30 pf v in = 0 v input capacitance nmi ? ? 30 pf f = 1 mhz all input pins except res and nmi ? ? 15 pf t a = 25c current consumption * 2 normal operation i cc * 3 ?tbd v cc = 5.0 v tbd v cc = 5.5 v ma f = 20 mhz sleep mode ? tbd v cc = 5.0 v tbd v cc = 5.5 v ma f = 20 mhz all modules stopped ? tbd ? ma f = 20 mhz, v cc = 5.0 v (reference values) medium- speed mode ( /32) ? tbd ? ma f = 20 mhz, v cc = 5.0 v (reference values) standby ? tbd tbd a t a 50c mode ? ? tbd a 50c < t a analog power supply during a/d conversion al cc ?2.54.0maav cc = 5.0 v current idle ? ? 5.0 a ram standby voltage v ram 2.0??v notes: 1. if the a/d converter is not used, do not leave the av cc , and av ss pins open. apply a voltage between 4.0 v and 5.5 v to the av cc pin by connecting them to v cc , for instance. 2. current consumption values are for v ih = v cc (extal), av cc (ports 4 and 9), or v cc (other), and v il = 0 v, with all output pins unloaded and the on-chip mos pull-up transistors in the off state. 3. i cc depends on v cc and f as follows: i cc (max.) = tbd (normal operation) i cc (max.) = tbd (sleep mode) rev. 0.5, 03/03, page 420 of 438 table 18.3 permissible output currents conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * item symbol min. typ. max. unit permissible output low current (per pin) all output pins v cc = 4.5 to 5.5 v i ol ??10ma permissible output low current (total) total of all output pins v cc = 4.5 to 5.5 v i ol ? ? 100 ma permissible output high current (per pin) all output pins v cc = 4.5 to 5.5 v ?i oh ??2.0ma permissible output high current (total) total of all output pins v cc = 4.5 to 5.5 v ?i oh ??30ma note: * to protect chip reliability, do not exceed the output current values in table 18.3. 18.3 ac characteristics figure 18.1 shows the test conditions for the ac characteristics. 5v r l r h c lsi output pin c=30pf: all ports r l = 2.4k ? r h =12 ? input/output timing measurement levels ? low level : 0.8v high level : 2.0v figure 18.1 output load circuit rev. 0.5, 03/03, page 421 of 438 18.3.1 clock timing table 18.4 lists the clock timing table 18.4 clock timing conditions : v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, = 4 mhz to 24 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item symbol min. max. unit test conditions clock cycle time t cyc 41.6 250 ns figure 18.2 clock high pulse width t ch tbd ? ns clock low pulse width t cl tbd ? ns clock rise time t cr ?tbdns clock fall time t cf ?tbdns oscillation stabilization time at reset (crystal) t osc1 20 ? ms figure 18.3 oscillation stabilization time in software standby (crystal) t osc2 8 ? ms figure 18.3 external clock output stabilization delay time t dext 2 ? ms figure 18.3 t cr t cl t cf t ch t cyc figure 18.2 system clock timing rev. 0.5, 03/03, page 422 of 438 t osc1 t osc1 extal v cc t dext t dext figure 18.3 oscillation stabilization timing 18.3.2 control signal timing table 18.5 lists the control signal timing. table 18.5 control signal timing conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, = 4 mhz to 24 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item symbol min. max. unit test conditions res setup time t ress 200 ? ns figure 18.4 res pulse width t resw 20 ? t cyc nmi setup time t nmis 150 ? ns figure 18.5 nmi hold time t nmih 10 ? ns nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time t irqs 150 ? ns irq hold time t irqh 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? ns rev. 0.5, 03/03, page 423 of 438 t resw t ress t ress figure 18.4 reset input timing t irqs edge input t irqh t nmis t nmih t irqs level input nmi (i = 0 to 5) t nmiw t irqw figure 18.5 interrupt input timing rev. 0.5, 03/03, page 424 of 438 18.3.3 timing of on-chip peripheral modules table 18.6 lists the timing of on-chip peripheral modules. table 18.6 timing of on-chip peripheral modules conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v, = 4 mhz to 24 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item symbol min. max. unit test conditions i/o port output data delay time t pwd ? 40 ns figure 18.6 input data setup time t prs 25 ? input data hold time t prh 25 ? tpu timer output delay time t tocd ? 40 ns figure 18.7 timer input setup time t tics 25 ? timer clock input setup time t tcks 25 ? ns figure 18.8 timer clock single edge t tckwh 1.5 ? t cyc pulse width both edges t tckwl 2.5 ? sci input clock asynchro- nous t scyc 4?t cyc figure 18.9 cycle synchro- nous 6? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?1.5t cyc input clock fall time t sckf ?1.5 transmit data delay time t txd ? 40 ns figure 18.10 receive data setup time (synchronous) t rxs 40 ? receive data hold time (synchronous) t rxh 40 ? rev. 0.5, 03/03, page 425 of 438 item symbol min. max. unit test conditions a/d converter trigger input setup time t trgs 30 ? ns figure 18.11 hcan * transmit data delay time t htxd ? 80 ns figure 18.12 transmit data setup time t hrxs 80 ? transmit data hold time t hrxh 80 ? note: * the hcan input signal is asynchronous. however, its state is judged to have changed at the rising-edge (two clock cycles) of the ck clock signal shown in figure 18.12. the hcan output signal is also asynchronous. its state changes based on the rising-edge (two clock cycles) of the ck clock signal shown in figure 18.12. port 1, 4, 9 a to d, f (read) t prs t 1 t 2 t pwd t prh port 1, a to d, f (write) figure 18.6 i/o port input/output timing t tics t tocd output compare output * input capture input * note : * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 18.7 tpu input/output timing rev. 0.5, 03/03, page 426 of 438 t tcks t tcks tclka to tclkd t tckwh t tckwl figure 18.8 tpu clock input timing t scyc t sckr t sckw sck0 to sck2 t sckf figure 18.9 sck clock input timing sck0 to sck2 txd0 to txd2 (transmit data) rxd0 to rxd2 (receive data) t txd t rxh t rxs figure 18.10 sci input/output timing (clocked synchronous mode) t trgs figure 18.11 a/d converter external trigger input timing rev. 0.5, 03/03, page 427 of 438 v ol v ol htxd (transmit data) hrxd (receive data) t htxd t hrxs t hrxh figure 18.12 hcan input/output timing 18.4 a/d conversion characteristics table 18.7 lists the a/d conversion characteristics. table 18.7 a/d conversion characteristics conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0v, = 4 mhz to 24 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) item min. typ. max. unit resolution 10 10 10 bits conversion time 10 ? 200 s analog input capacitance ? ? 20 pf permissible signal-source impedance ? ? 5 k ? nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization ? 0.5 ? lsb absolute accuracy ? ? 4.0 lsb rev. 0.5, 03/03, page 428 of 438 18.5 flash memory characteristics table 18.8 lists the flash memory characteristics. table 18.8 flash memory characteristics conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = 0 to +75c (programming/erasing operating temperature range) item symbol min. typ. max. unit test condition programming time * 1, * 2, * 4 t p ? 10 200 ms/128 bytes erase time * 1, * 3, * 5 t e ? 100 1200 ms/block reprogramming count n wec ? ? 100 times programming wait time after swe bit setting * 1 t sswe 11?s wait time after psu1 bit setting * 1 t spsu 50 50 ? s wait time after p1 bit setting * 1, * 4 t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait t sp10 8 10 12 s additional- programming time wait wait time after p1 bit clear * 1 t cp 55?s wait time after psu1 bit clear * 1 t cpsu 55?s wait time after pv1 bit setting * 1 t spv 44?s wait time after h'ff dummy write * 1 t spvr 22?s wait time after pv1 bit clear * 1 t cpv 22?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1, * 4 n ? ? 1000 times erase wait time after swe bit setting * 1 t sswe 11?s wait time after esu1 bit setting * 1 t sesu 100 100 ? s wait time after e1 bit setting * 1, * 5 t se 10 10 100 ms erase time wait wait time after e1 bit clear * 1 t ce 10 10 ? s wait time after esu1 bit clear * 1 t cesu 10 10 ? s wait time after ev1 bit setting * 1 t sev 20 20 ? s wait time after h'ff dummy write * 1 t sevr 22?s wait time after ev1 bit clear * 1 t cev 44?s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1, * 5 n 12 ? 120 times rev. 0.5, 03/03, page 429 of 438 notes: 1. make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. programming time per 128 bytes (shows the total period for which the p1 bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e1 bit in flmcr1 is set. it does not include the erase verification time.) 4. to specify the maximum programming time value (tp (max.)) in the 128-bytes programming algorithm, set the max. value (1000) for the maximum programming count (n). the wait time after p1 bit setting should be changed as follows according to the value of the programming counter(n). programming counter(n) = 1 to 6: tsp30 = 30 s programming counter(n) = 7 to 1000: tsp200 = 200 s [in additional programming] programming counter(n) = 1 to 6: tsp10 = 10 s 5. for the maximum erase time (te(max.)), the following relationship applies between the wait time after e1 bit setting (tse) and the maximum erase count (n): te (max.) = wait time after e1 bit setting (tse) x maximum erase count (n) to set the maximum erase time, the values of (tse) and (n) should be set so as to satisfy the above formula. examples: when tse = 100 ms, n = 12 times when tse = 10 ms, n = 120 times rev. 0.5, 03/03, page 430 of 438 rev. 0.5, 03/03, page 431 of 438 appendix a. i/o port states in each pin state port name mcu operating mode reset hardware standby mode software standby mode program execution state sleep mode port 1 7 t t keep i/o port port 47ttti nput port port 97ttti nput port port a 7 t t keep i/o port port b 7 t t keep i/o port port c 7 t t keep i/o port port d 7 t t keep i/o port pf7 7 t t [ddr = 0] t [ddr = 1] h [ddr = 0] t [ddr = 1] clock output pf6 pf5 pf4 pf3 pf2 pf1 pf0 7 t t keep i/o port htxd 7 h t h output hrxd 7 input t t input legend h: high level t: high impedance keep: input port becomes high-impedance, output port retains state rev. 0.5, 03/03, page 432 of 438 b. product code lineup product classification type name model marking package (code) h8s/2615 flash memory version HD64F2615 HD64F2615 masked rom version * hd6432615 hd6432615 80-pin qfp (fp-80q) note: * in planning rev. 0.5, 03/03, page 433 of 438 c. package dimensions the package dimension that is shown in the hitachi semiconductor package data book has priority. hitachi code jedec jeita mass (reference value) fp-80q ? conforms 1.2 g * dimension including the plating thickness base material dimension 60 0? ? 8? 0.10 0.12 m 17.2 0.2 41 61 80 1 20 40 21 17.2 0.2 * 0.32 0.08 0.65 3.05 max 1.6 0.8 0.2 14 2.70 * 0.17 0.05 0.10 +0.15 ?0.10 0.83 0.30 0.06 0.15 0.04 unit: mm figure c.1 fp-80q package dimensions rev. 0.5, 03/03, page 434 of 438 rev. 0.5, 03/03, page 435 of 438 index 16-bit timer pulse unit (tpu) .............. 113 buffer operation ................................. 157 cascaded operation ............................ 161 free-running count operation.............. 151 phase counting mode......................... 167 pwm modes....................................... 162 synchronous operation....................... 156 toggle output...................................... 152 waveform output by compare match 152 a/d converter ........................................ 311 a/d converter activation................... 175 a/d trigger input................................. 110 conversion time................................. 319 external trigger.................................. 321 scan mode .......................................... 318 single mode........................................ 318 address map............................................. 49 address space........................................... 16 addressing modes .................................... 37 absolute address.................................. 38 immediate ............................................. 39 memory indirect ................................... 39 program-counter relative .................... 39 register direct ...................................... 37 register indirect.................................... 37 register indirect with displacement..... 37 register indirect with post-increment .. 38 register indirect with pre-decrement... 38 bcc ...................................................... 25, 33 bit rate ................................................... 296 bus cycle................................................... 81 clock pulse generator ............................ 351 condition field ......................................... 36 condition-code register (ccr)............... 20 cpu operating modes.............................. 12 advanced mode.................................... 13 normal mode ........................................12 data direction register ...............................85 data register ..............................................85 effective address ......................................40 effective address extension .....................36 exception handling...................................51 interrupts ...............................................56 reset exception handling.....................53 stack status ...........................................58 traces....................................................56 trap instruction.....................................57 exception handling vector table.............52 extended control register (exr).............19 general registers ......................................18 hitachi controller area network (hcan)...................................................265 11 consecutive recessive bits...............293 arbitration field...........................300, 303 buffer segment ....................................296 configuration mode ............................293 control field ........................................300 data field.............................................300 data frame...........................................303 hcan halt mode ...............................306 hcan sleep mode .............................305 mailbox .......................................289, 291 message control (mc0 to mc15) ......289 message data (md0 to md15)...........291 message transmission cancellation .....300 message transmission method...........298 remote frame ......................................304 remote transmission request bit .........304 unread message overwrite ..................304 input pull-up mos ....................................85 rev. 0.5, 03/03, page 436 of 438 instruction set........................................... 25 arithmetic operations instructions....... 28 bit manipulation instructions ............... 31 block data transfer instructions .......... 35 branch instructions ............................... 33 data transfer instructions .................... 27 logic operations instructions............... 30 shift instructions................................... 30 system control instructions.................. 34 interrupt control modes ........................... 72 interrupt controller................................... 61 interrupt exception handling vector table .................................................................. 69 interrupt mask bit..................................... 20 interrupt mask level .................................. 19 interrupt priority register (ipr)................. 61 interrupts adi ..................................................... 321 ers0/ovr0 ....................................... 307 nmi ................................................ 68, 79 rm0 .................................................... 307 rm1 .................................................... 307 sle0 ................................................... 307 tci0v................................................. 174 tci1u................................................. 174 tci1v................................................. 174 tci2u................................................. 174 tci2v................................................. 174 tci3v................................................. 174 tci4u................................................. 174 tci4v................................................. 174 tci5u................................................. 174 tci5v................................................. 174 tgi0a................................................. 174 tgi0b................................................. 174 tgi0c................................................. 174 tgi0d................................................. 174 tgi1a................................................. 174 tgi1b................................................. 174 tgi2a................................................. 174 tgi2b................................................. 174 tgi3a................................................. 174 tgi3b ................................................. 174 tgi3c ................................................. 174 tgi3d................................................. 174 tgi4a................................................. 174 tgi4b ................................................. 174 tgi5a................................................. 174 tgi5b ................................................. 174 wovi.................................................. 200 mac instruction ....................................... 46 memory cycle ........................................... 81 multiply-accumulate register (mac) ..... 21 on-board programming.......................... 339 open-drain control register ....................... 85 operating mode selection......................... 45 operation field ......................................... 36 pll circuit ............................................. 357 port register............................................... 85 power-down modes direct transitions................................ 378 subactive mode .................................. 378 subsleep mode.................................... 377 watch mode........................................ 376 program counter (pc) .............................. 19 program/erase protection ....................... 349 programmer mode .................................. 350 register field ............................................ 36 registers aback....................... 277, 382, 395, 407 adcr ......................... 317, 394, 405, 415 adcsr ....................... 315, 394, 405, 415 addr ......................... 314, 394, 405, 415 bcr ............................ 271, 382, 395, 407 brr ............................ 218, 393, 405, 414 ebr1........................... 337, 394, 405, 415 flmcr1 ..................... 336, 394, 405, 415 flmcr2 ..................... 337, 394, 405, 415 flpwcr..................... 339, 394, 405, 415 gsr............................. 269, 382, 395, 407 rev. 0.5, 03/03, page 437 of 438 hcanmon................ 291, 390, 402, 412 ier................................ 65, 390, 402, 412 imr............................. 284, 382, 395, 407 ipr ................................ 64, 392, 403, 413 irr.............................. 280, 382, 395, 407 iscr ............................. 66, 390, 402, 412 isr ................................ 68, 390, 402, 412 lafmh ...................... 287, 382, 395, 407 lafml....................... 287, 382, 395, 407 lpwrcr.................... 367, 390, 402, 412 mbcr......................... 273, 382, 395, 407 mbimr....................... 283, 382, 395, 407 mc .............................. 289, 382, 395, 407 mcr ........................... 268, 382, 395, 407 md.............................. 291, 386, 398, 409 mdcr........................... 46, 390, 402, 412 mstpcr..................... 368, 390, 402, 412 p1ddr.......................... 88, 390, 402, 412 p1dr ............................ 88, 392, 403, 413 paddr......................... 93, 390, 402, 412 padr............................ 94, 392, 403, 413 paodr......................... 95, 391, 402, 413 papcr.......................... 95, 391, 402, 412 pbddr ......................... 97, 390, 402, 412 pbdr............................ 97, 392, 403, 413 pbodr ......................... 99, 391, 402, 413 pbpcr.......................... 98, 391, 402, 412 pcddr ....................... 101, 390, 402, 412 pcdr.......................... 102, 392, 403, 413 pcodr ....................... 104, 391, 402, 413 pcpcr........................ 103, 391, 402, 412 pdddr....................... 106, 390, 402, 412 pddr.......................... 107, 392, 403, 413 pdpcr........................ 108, 391, 402, 412 pfddr ....................... 108, 391, 402, 412 pfdr .......................... 109, 392, 403, 413 port1 .......................... 89, 394, 406, 415 port4 .......................... 92, 394, 406, 415 port9 .......................... 92, 394, 406, 415 porta ......................... 94, 394, 406, 415 portb ......................... 98, 394, 406, 415 portc ....................... 103, 394, 406, 415 portd ....................... 107, 394, 406, 415 portf ........................ 110, 394, 406, 415 ramer ...................... 338, 392, 403, 413 rdr ............................ 206, 393, 405, 414 rec............................. 285, 382, 395, 407 rfpr........................... 279, 382, 395, 407 rsr .....................................................206 rstcsr...................... 197, 393, 404, 414 rxpr .......................... 278, 382, 395, 407 sbycr........................ 365, 390, 402, 412 sckcr........................ 352, 390, 402, 412 scmr ......................... 217, 393, 405, 414 scr ............................. 210, 393, 405, 414 smr ............................ 207, 393, 405, 414 ssr ............................. 212, 393, 405, 414 syscr .......................... 46, 390, 402, 412 tcnt .......................... 193, 393, 404, 414 tcr............................. 120, 392, 404, 414 tcsr........................... 193, 393, 404, 414 tdr............................. 206, 393, 405, 414 tec ............................. 285, 382, 395, 407 tgr............................. 148, 392, 404, 414 tier............................ 144, 392, 404, 414 tior ........................... 127, 392, 404, 414 tmdr ......................... 125, 392, 404, 414 tsr ............................. 145, 392, 404, 414 tstr........................... 148, 392, 403, 413 tsyr .......................... 149, 392, 403, 413 txack....................... 276, 382, 395, 407 txcr.......................... 275, 382, 395, 407 txpr .......................... 274, 382, 395, 407 umsr ......................... 286, 382, 395, 407 reset..........................................................53 rom .......................................................329 boot mode ..........................................340 emulation ............................................343 erase/erase-verify ..............................347 erasing units........................................334 program/program-verify ....................345 programming units ..............................334 programming/erasing in user program mode ...................................................342 rev. 0.5, 03/03, page 438 of 438 serial communication interface (sci) ... 203 asynchronous mode ........................... 225 bit rate ................................................ 218 break................................................... 263 framing error ...................................... 232 mark state........................................... 263 overrun error ...................................... 232 parity error.......................................... 232 stack pointer (sp) ..................................... 18 time quanta (tq)................................... 297 trace bit ................................................... 19 trapa instruction ................................... 57 watchdog timer interval timer mode ........................... 200 overflows............................................ 198 watchdog timer (wdt)......................... 191 h8s/2615 series hardware manual ? ? ? ? preliminary ? ? ? ? publication date: 0.5th edition, march 2003 published by: business operation division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2003. all rights reserved. printed in japan. |
Price & Availability of HD64F2615
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |